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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About Allegro PCB Editor IPC 2581 Data Transfer Standard? 16.6 Has It

The 16.6 Allegro PCB Editor now has IPC 2581 data transfer capabilities. Thanks to…

• 10 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , 16.6 , layer stacks , artwork , SPB , interfaces , PCB Editor , Layout , design , PCB design , Grzenia , Allegro PCB Editor , Standards based Interfaces , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays - Improving Hardware Verification with Accelerated Verification…

In this week's Whiteboard Wednesdays, Tom Hackett talks about Accelerated Verification…

• less than a min read
AVIP , accelerated VIP , Verification IP , Whiteboard Wednesdays , VIP , hardware verification

System, PCB, & Package Design 

Build Components Quickly and Easily with Pre-Defined Escape Routing Using Cadence…

When it comes to designing a dense flip-chip die - or even defining a BGA for a complex…

• 5 min read
Allegro package design , reusable tiles , EDA , package design , SiP Layout , substrate design tools

RF Engineering

Distortion Summary in New CDNLive YouTube Video and at IEEE IMS2014 Next Week!

Hi Folks, Check out this great new video on YouTube: CDNLive SV 2014: PMC Improves…

• less than a min read
Wilsey , Spectre RF , spectreRF , RF design , harmonic balance , Distortion

Verification

PCIe Gen4 LIVE Demo at PCI-SIG DevCon Next Week

The PCI-SIG has (FINALLY) released the PCIe 4.0 rev 0.3 specification for members…

• 1 min read
Verification IP , IP , PCI Express 3.0 , Gen3 , NVMe , VIP , M-PCIe , MPCIe , PCIe , PCIe Gen3 , PCI-SIG

Whiteboard Wednesdays

Whiteboard Wednesdays—Trends in the Mobile Memory World

In this week's Whiteboard Wednesdays, Kishore Kasamsetty discusses the low-power…

• less than a min read
Whiteboard Wednesdays , Memory , LPDDR4 , mobile , LPDDR3

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Offset Routing? 16.6 Has a Few New Enhancements

The Add Connect with Offset command in Allegro PCB Editor 16.6 is designed to primarily…

• 4 min read
Routing , signal grouping , 16.6 , SPB , PCB Editor , differential pair , Layout , group routing , Allegro

Verification

DAC 2014—ESL Design Is Dead... Long Live ESL!

Next week the EDA industry is getting together in San Francisco for Design Automation…

• 20 min read
DAC , Frank Schirrmeister , ESL

Analog/Custom Design

Virtuosity: 19 Things I Learned in April 2014 by Browsing Cadence Online Support

Plenty to keep you busy this month. Lots of RAKs, videos, and new Quick Start Guides…

• 4 min read
Variability Aware Design , AMS , Virtuoso online support , Routing , ADE XL , Virtuoso Analog Design Environment , Spectre , Schematic Editor , Virtuosity , Virtuoso Layout Suite XL

SoC and IP

IP at DAC? You Bet!

This year, the Design Automation Conference (June 1-5 in San Francisco) has put a…

• 1 min read
Verification IP , Design IP , VIP , DAC2014

RF Engineering

How to Specify Phase Noise as an Instance Parameter in Spectre Sources (e.g. vsource…

Last year, I wrote a blog post entitled Modeling Oscillators with Arbitrary Phase…

• 1 min read
Spectre RF , phase noise , spectreRF , analogLib , port , noise profiles

Whiteboard Wednesdays

Whiteboard Wednesdays - Taking Command of MIPI PHYs - M-PHY

In this week's Whiteboard Wednesdays, the second installment of a three-party series…

• less than a min read
mobile devices , Whiteboard Wednesdays , MIPI PHYs , M-PHY

SoC and IP

400G Task Force, 100G Backplane Project and Other Highlights from IEEE 802.3 Ethernet…

Here is another report from an IEEE 802.3 Ethernet standards meeting, this time held…

• 2 min read
25G Ethernet , Ethernet standards , Automotive Ethernet , IEEE 802.3 , 100G backplane , 400G

Computational Fluid Dynamics

NASA Glenn Research Center: Integrated Fluid Dynamics – Acoustics Simulation Approach…

An innovative computational approach, integrating mesh generation, CFD simultaneous…

• less than a min read

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Show Measure for Dual Units? 16.6 Has It!

The Allegro PCB Editor 16.6 ‘Show Measure’ command now displays results in database…

• 1 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , Routing , electrical constraints , SPB , PCB Editor , Layout , design , PCB design , physical layout design , Allegro PCB Editor , PCB Capture , Allegro

Analog/Custom Design

High Yield Analysis and Optimization - How to Design the Circuit to Six Sigma

Why high yield analysis? One failed memory cell out of millions cells will cause…

• 2 min read
Six Sigma , Virtuoso , Circuit Design , analog design , high yield analysis

Verification

sync and wait Actions vs. Temporal Struct and Unit Members

Using sync on a temporal expression (TE), does not guarantee that the execution will…

• 2 min read
AF , events , IntelliGen , Specman , units , e code , temporal expressions , Funcional Verification

Whiteboard Wednesdays

Whiteboard Wednesdays - Promises and Challenges of DDR4 Memory Technology

In this week's Whiteboard Wednesdays, Kishore Kasamsetty provides a history on DDR4…

• less than a min read
memory protocols , Whiteboard Wednesdays , DDR4 , DDR3

RF Engineering

See Cadence RF Technologies at IEEE International Microwave Symposium 2014

RF Enthusiasts, Come connect with Cadence RF experts and discover the latest advances…

• less than a min read
RF Simulation , IMS , RFIC , Spectre RF , Virtuoso , International Microwave Symposium , IEEE
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