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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

SoC and IP

IEEE 802.3 -- Standardizing the Next Generation of Ethernet PHYs

I attended the IEEE 802.3 standards meeting in York, England recently. Over 200 people…

• 1 min read
Design IP , 802.3bs , PHY , 400Gpbs , 40Gbps , Automotive Ethernet , 100Gbps , IEEE 802.3 , Ethernet , Marris , semiconductor IP , Ethernet PHYs , data centers

Digital Design

Five-Minute Tutorial: EM Model Files Revisited

Back in January, I posted a Five-Minute Tutorial about creating EM Model files .…

• 2 min read
EDI , qrcTechFile , EM Model , ICT , Techgen , iRCX , EPS , digital implementation , EM Model File , Power Analysis , EM , five minute tutorial

Analog/Custom Design

Virtuosity: 15 Things I Learned in August by Browsing Cadence Online Support

Our folks over in Physical Design have been busy churning out helpful Rapid Adoption…

• 3 min read
Rapid Adoption Kit , Virtuoso , Spectre , Virtuosity

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Shape Contraction and Expansion? Check Out 16

The 16.6 Allegro PCB Editor includes new enhancements to effectively manage shape…

• 3 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , 16.6 , PCB Editor , Layout , design , PCB design , Grzenia , physical layout design , Allegro PCB Editor , Allegro , etch shapes

System, PCB, & Package Design 

Create Optimum Pin Assignments for FPGAs on PCBs - Part 2 of 2

In part 1 of this blog , I discussed a scenario that PCB designers working with FPGA…

• 5 min read
FPGA: ASIC Prototype , FPGA-PCB Co-Design , FPGA System Planner , FPGAs , FSP , pinswap , "PCB design" , OrCAD , PCB design , pin planning , pin swap , FPGA , Allegro , FPGA Pin Assignment , FPGA: PCB

Verification

HDMI 2.0 – Ushering in the Next Generation of Ultra HD TV

The future of television is being defined by two key technologies: organic light…

• 2 min read
Verification IP , HDMI 2.0 , Ultra HD , 4K TV , cadence , VIP , HDTV , SoCs

Analog/Custom Design

SKILL for the Skilled: Visiting All Permutations

In this posting I want to look at several ways of generating permutations of a list…

• 8 min read
Team SKILL , programming , Jim Newton , IC615 , SKILL for the Skilled , permutations , Lisp , SKILL++ , SKILL

System, PCB, & Package Design 

How Do You Route Your Highly Constrained PCBs? (Part 1 of 2)

How routing is performed to meet the design intent of designers and engineers seems…

• 4 min read
interface aware design , DDR2 , Constraint-driven PCB Design flow , interconnects , Allegro 16.6 , Routing , route quality , 16.6 routing , interface definitions , interfaces , PCB Editor , PCB routing , Allegro router , "PCB design" , PCB design , Constraint Driven PCB routing , DDR3

Analog/Custom Design

SKILL for the Skilled: How to Copy a Hash Table

In this posting I want to look at ways to copy a hash table in SKILL. There are several…

• 8 min read
Team SKILL , programming , hash table , Jim Newton , IC615 , SKILL for the Skilled , Lisp , SKILL++ , SKILL

Verification

Configurable Specman Messaging Webinar Archive Available Now

Configurable Specman Messaging for Improved Productivity Webinar Archive Available…

• 1 min read
IEEE 1647 , Specman/e , AVS , Functional Verification , Specman e , Testbench simulation , Incisive Enterprise Simulator , e-language , configurable messaging , EDA , e , webinar , e language , Specman messaging , Specman C

System, PCB, & Package Design 

Create Optimum Pin Assignments for FPGAs on PCBs - Part 1 of 2

In most FPGA-based boards, the PCB designer is on his own -- with little help from…

• 5 min read
FPGA: ASIC Prototype , FPGA-PCB Co-Design , FPGA System Planner , FPGAs , FSP , pinswap , "PCB design" , PCB design , pin planning , pin swap , FPGA , FPGA Pin Assignment , FPGA: PCB

System, PCB, & Package Design 

What's Good About FSP’s Allegro PCB Editor Board Import? 16.6 Has It!

The Allegro FPGA System Planner (FSP) has the ability in the 16.6 release to import…

• 5 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , cadence , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , Taray , FPGAs , SPB , PCB Editor , Layout , design , FSP , "PCB design" , PCB design , Grzenia , Allegro PCB Editor , FPGA , Allegro , FPGA: PCB

System, PCB, & Package Design 

Enhance Your Packaging Documentation Outputs with the New SKILL Spreadsheet API Tools…

Spreadsheets, we all use them, and many of us do so daily. They are an efficient…

• 3 min read
IC Packaging and SiP Design , SiP , IC Package , IC Packaging , packaging , Digital SiP design , 16.6 , IC Packaging and SiP , IC package design , APD , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout , IC Package Physical layout and co-design , cavity

Verification

Getting Ready for ESL with Emulation!

Next week on Monday, August 19th, Gary Smith will run a webinar called " ESL - Are…

• 2 min read
Low Power , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Acceleration , System to Silicon Verification , Dynamic Power Analysis , System Design and Verification , System Development Suite , embedded software , Gary Smith , GSEDA , Palladium XP , Emulation , Atrenta , Schirrmeister , ESL , low power optimization

Analog/Custom Design

Virtuosity: 16 Things I Learned in July by Browsing Cadence Online Support

Feeling a bit lazy this month, but even without digging too deeply, I could find…

• 2 min read
AMS , mixed-signal simulators , custom/analog , Virtuoso Space-based Router , Routing , Rapid Adoption Kit , MMSIM , Mixed-Signal , Virtuoso , Schematic Editor , Virtuosity , AMS simulation , mixed signal , Modeling , Custom IC Design , space based router

System, PCB, & Package Design 

What's Good About Allegro PCB Enhanced Object Filtering? See for yourself in 16.6

The 16.6 Allegro PCB Editor release provides enhanced Object Filtering to control…

• 2 min read
PCB , PCB Layout and routing , Cadence Design Systems , diff pairs , constraint databases , Allegro GUI , Allegro 16.6 , cadence , DEHDL , electrical constraints , object visibility layers , 16.6 , property , diff pair , SPB , PCB Editor , Constraint Manager , Design Entry HDL , differential pair , Layout , Xnets , design , "PCB design" , PCB design , Design Entry , Constraints , Grzenia , Allegro PCB Editor , differential pairs , Differential Pair Support , ConceptHDL , PCB Capture , Allegro

System, PCB, & Package Design 

What's Good About AMS Schematic Undo? It’s in the 16.6 Release!

Just a very brief post this week on a new AMS Simulator (PSpice) capability. The…

• less than a min read
capture , AMS , Allegro 16.6 , cadence , AMS simulator , OrCAD Capture , 16.6 , Capture CIS , PSPICE , OrCAD , AMS simulation , Grzenia

System, PCB, & Package Design 

What's Good About RF PCB Libraries? 16.6 Has a Few New Enhancements!

There have been a few new library level enhancements made to 16.6 Allegro RF PCB…

• 1 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , RF PCB , cadence , Agilent , 16.6 , SPB , PCB Editor , Layout , design , PCB design , Grzenia , physical layout design , Allegro PCB Editor , Librarians , Agilent ADS , library

System, PCB, & Package Design 

What's Good About PCB SI Channel Analysis? 16.6 Has Many New Enhancements!

There are several new enhancements associated with the 16.6 PCB SI Channel Analysis…

• 5 min read
PCB SI , SI , Cadence Design Systems , Allegro 16.6 , cadence , Signal Intregrity , SigXP UI , 16.6 , "PCB SI" , High Speed , SPB , signal integrity analysis , Signal Integrity , "channel analysis" , design , "PCB design" , Allegro PCB SI , Grzenia , SI analysis and modeling
CDNS - Fix Layout Hompage