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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About DEHDL’s Page Search? The Secret's in the 16.5 Release!

Prior to the 16.5 release, the search capabilities in Allegro Design Entry HDL (DEHDL…

• 1 min read
DEHDL find , page search , hierarchy , DEHDL , flat schematics , hierarchical schematics , Allegro 16.5 , SPB , Design Entry HDL , Find result , Front-end PCB design , design , PCB design , Design Entry , Grzenia , SPB16.5 , ConceptHDL , Schematic , Allegro

System, PCB, & Package Design 

What's Good About PCB SI Static IR Drop Analysis? 16.5 Has Many New Enhancements

In the Allegro PCB SI 16.5 release, static IR drop analysis has been integrated into…

• 3 min read
PCB SI , PI , PCB PI , PDN , IBIS , SigXP UI , Power Integrity , "PCB SI" , High Speed , Allegro 16.5 , IBIS-AMI , SPB , design , Allegro PCB SI , 16.5 , "PCB PI" , Grzenia , SPB16.5 , SI analysis and modeling , IR drop , power , 3D viewer , Allegro

Analog/Custom Design

ARM-Based Microcontrollers using Cadence’s Mixed-Signal Solution

I recently came across a Wall Street Journal article, "ARM Chases Bigger Slice of…

• 2 min read
DAC , microcontrollers , Demo , Cortex-M , MCUs , Virtuoso , Cortex-M0 , incyte , fuel injection system , System Design Kit , micro-controllers , ARM , Balasubramanian

System, PCB, & Package Design 

What's Good About Allegro PCB Editor PDF Publisher? See for Yourself in 16.5!

Starting with release 16.5, it is possible to export data from Allegro PCB Editor…

• 2 min read
PCB , PCB Layout and routing , Allegro GUI , PDF , artwork , property , Allegro 16.5 , SPB , PDF Publisher , PCB Editor , Layout , design , PCB design , Grzenia , SPB16.5 , Allegro PCB Editor , Allegro

Verification

Shameless Promotion: Free Club Formal San Jose (with Lunch) on Wednesday 10/17

Please join Team Verify and other design and verification engineers at the next …

• 1 min read
ABV , Formal Analysis , formal , formal apps , Vigyan Singhal , Chris Komar , Oski Technology , Club Formal

Verification

iPhone5 Differentiation is Chip Design

In case you may have missed it, Apple recently launched a new iPhone. As per the…

• 5 min read
High-Level Synthesis , Apple , TLM , RTL , android , iPhone5 , Samsung , SoC , C-to-Silicon , software , smartphones , ARM , ESL , iPhone , Audience

Verification

Using a Network File System with the Xilinx Zynq-7000 Virtual Platform

There are a number of ways to do embedded software development for Xilinx Zynq-7000…

• 5 min read
Ubuntu 12.04 , Zynq virtual platform , Network File System , Embedded Linux

Analog/Custom Design

SKILL for the Skilled: Part 3, Many Ways to Sum a List

In Part 1 and Part 2 of this series of posts, I showed a couple of ways to sum up…

• 4 min read
recursive functions , Team SKILL , Jim Newton , sum a list , SKILL for the Skilled , recursion , Virtuoso , Lisp , Custom IC Design , SKILL++

Verification

Accelerated VIP Delivers Value for Firmware/Driver Validation and Integration

Earlier this year, Cadence announced the expansion of its VIP Catalog to include…

• 2 min read
validation. , Driver , firmware , System Design & Verification

Verification

Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study…

Right up there with functional verification, the challenges of low power design and…

• 3 min read
uvm , Low Power , GoPro Hero2 , thermal verification , Functional Verification , MCAD , video , mechanical design automation , EDA , low-power design , thermal behavior , heat dissipation

System, PCB, & Package Design 

What's Good About ADW’s Flow Manager? Check out the 16.5 Release and See!

The 16.5 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide…

• 1 min read
PCB , data management , symbol editor , flow manager , Allegro Design Workbench , Library flow , Team design , Allegro 16.5 , Library and design data management , SPB , Design Entry HDL , design data management , symbol , design , PCB design , Design Entry , Grzenia , SPB16.5 , Librarians , library , ADW , Schematic , Allegro

Analog/Custom Design

SKILL for the Skilled: Part 2, Many Ways to Sum a List

In the previous posting, SKILL for the Skilled: Many Ways to Sum a List (Part 1 …

• 4 min read
Team SKILL , Jim Newton , sum a list , summing , Virtuoso , software development , SKILL++ , SKILL

Digital Design

Simple Steps to Debug DRC Violations Undetected in EDI System

You've placed and routed your design in the Encounter Digital Implementation (EDI…

• 4 min read
EDI , DRC , design rules , DRC signoff , LEF , Cadence Online Support , NanoRoute , encounter , Digital Implementation , Encounter Digital Implementation , Verify Geometry , PVS , DRC violations , debug DRC violations

Analog/Custom Design

Things You Didn't Know About Virtuoso: The (Setup) State of Things

Apologies for the long delay between articles (best intentions and all that). I last…

• 3 min read
Variability Aware Design , Analog Design Environment , Virtuoso IC6.1.5 , setup states , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , Custom IC Design

Analog/Custom Design

SKILL for the Skilled: Part 1, Many Ways to Sum a List

A while back I presented a one day SKILL++ seminar to a group of beginner and advanced…

• 3 min read
Jim Newton , sum a list , summing , Virtuoso , apply , software development , SKILL++ , sumlist , SKILL

Verification

UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation…

• 2 min read
AF , uvm , Specman , BFM , Testflow , Functional Verification , testflow phases , e language , team specman , sequences , Reset mechanism , Shneydor , verification , sequence driver

Verification

What Does it Take to Migrate from e to UVMe?

So you are developing your verification environment in e , and like everyone else…

• 3 min read
IEEE 1647 , SystemVerilog , scoreboard , uvm , Specman , Specman/e , UVM e , vr_ad , UVM-e , advanced verification , e language , UVC , SCE-MI , team specman , Constraints , Aspect Oriented Programming , sequences , Incisive Enterprise Simulator (IES) , Shneydor , AOP

System, PCB, & Package Design 

What's Good About DEHDL’s Find Functionality? The Secret's in the 16.5 Release!

The current Allegro Design Entry HDL (DEHDL) Page Search toolbar works only on the…

• 3 min read
DEHDL find , page search , hierarchy , flat schematics , super filter , selection filters , property changes , Allegro 16.5 , Design Entry HDL , Find result , design , Design Entry , Grzenia , highlighting , SPB16.5 , ConceptHDL , PCB Capture , Schematic , Allegro

Verification

Introduction to the Linux Kernel Message System

One of the most common problem reports related to Virtual Platforms running Linux…

• 6 min read
Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , System Design and Verification , kernel messaging system , Andrews
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