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Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About Customer Support AppNotes? They Will Increase Your Productivity

Our Silicon Package Board (SPB) Customer Support team has initiated a new blog series…

• less than a min read
PCB , PCB Layout and routing , customer support , applications , Allegro 16.5 , Appnotes , PCB Editor , Allegro performance , Layout , design , PCB design , 16.5 , SPB16.5 , Allegro PCB Editor , application note , OrCAD PCB Editor , Online Support , Allegro

System, PCB, & Package Design 

Customer Support Recommended - Appnote on Increasing Performance in Allegro PCB …

While working on very large scale Printed Circuit Board (PCB) files that contain…

• 1 min read
COS , PCB , PCB Layout and routing , customer support , Performance Advisor , Support , Allegro 16.5 , PCB Editor , Allegro performance , Layout , Appnote , dbdoctor , PCB design , SPB16.5 , Allegro PCB Editor , application note , Online Support , Allegro

Verification

UVM Testflow Phase Debugging- Identifying Blocking Activities

UVM Testflow debugging capabilities have been recently enhanced through the addition…

• 1 min read
AF , uvm , Specman , methodology , Testflow , Functional Verification , testflow phase debugging , testflow phases , advanced verification , e language , blocking activities , IES-XL

Analog/Custom Design

Mixed-Signal Gets Clear Message in China

While most of my colleagues in the US were taking a nice break during the July 4…

• 3 min read
mixed-signal seminars , Beijing , AMS , China , mixed signal design , Technology on tour , mixed-signal ToT , mixed-signal methodology , mixed signal methodology , tech on tour , mixed signal solution , analog , Mixed-Signal , Shenzhen , mixed signal methodology guide , mixed signal , ARM , tech-on-tour , Shanghai , AMS Verification , mixed-signal verification

Digital Design

Improve Your Productivity With Rapid Adoption Kits (RAKs) for Encounter Digital Implementation…

As you know, Cadence Online Support is your 24/7 site for getting help and resolving…

• 2 min read
SoC-Encounter , Cadence On-Line Support , Low Power , Foundation Flow , DBTcl , EDI system , Signoff Analysis , Low-Power , EDI 11.1 , Cadence Online Support , NanoRoute , Silicon Realization , Digital Implementation , EDI system Encounter Digital Implementation System , CTS , Enouter Timing System , Rapid Adoption Kits , RAKs , SoC-Encounter dbGet dbSet

Verification

Using Flexible Specman License Searches

Until recently, Specman used to look for its licenses in the following strict, hardcoded…

• 2 min read
AF , Specman , new features , Functional Verification , licenses , license search , Incisive , e language , Specman licenses , verification , IES-XL

Verification

Adding Xilinx C Models to the Virtual Platform of the Zynq-7000 EPP

Today, I have a good article from Henry Von Bank of Posedge Software related to Zynq…

• 5 min read
Virtual System Platform , zynq , virtual platforms , TLM , posedge , IP-XACT , Henry Von Bank , virtual prototypes , VSP , RDF , SystemC , xilinx , ARM , FFT , Zynq virtual platform , Zynq-7000

System, PCB, & Package Design 

What's Good About Capture’s CIS INI Settings? Look to SPB16.5 and See!

This week, I'm providing a very short blog. While the content is brief and simple…

• less than a min read
capture , "capture CIS" , OrCAD Capture Marketplace , OrCAD Capture , Capture CIS , Capture-CIS , Allegro 16.5 , SPB , design , OrCAD , Design Entry , SPB16.5 , PCB Capture , Schematic

Verification

DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on Functional…

Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University…

• 1 min read
DAC , uvm , Joe Hupcey III , interview , Functional Verification , video , Dr. Kerstin Eder , University of Bristol , DAC 2012

Verification

C-to-Silicon Japan User Group and Ikegami Production Experience

We have been seeing some rapid growth in adoption of C-to-Silicon Compiler high-level…

• 2 min read
High-Level Synthesis , customers , Maesato , japan , Japan user group , Ikegami , SystemC , C-to-Silicon Compiler , Synthesis , Virtex-6 , HLS , ESL , FPGA

Verification

DAC2012: Xilinx Zynq-7000 - From RTL to Success with Emulation

It is nice to see when visions get closer to reality. When Cadence announced its…

• 4 min read
DAC , Virtual System Platform , zynq , cadence , Acceleration , debug , Functional Verification , System Design and Verification , System Development Suite , embedded software , Emulation , virtual prototype , Software Development and Debug , firmware , Performance Analysis , xilinx , DAC 2012 , Design Automation Conference , system integration

Verification

Video: DAC 2012 Update on AMIQ’s DVT IDE – New RTL Design Work Flow Support

Readers of this blog and of Team Specman will recall that Integrated Development…

• less than a min read
DAC , eclipse , Joe Hupcey III , Cristian Amitroaie , DVT , AMIQ , DAC 2012 , RTL design , integrated development environment , IDE

Verification

SystemC TLM-2.0 Virtual Platform Direct Memory Interface (DMI) Performance Impac…

One of the most interesting concepts in SystemC TLM-2.0 is the concept of Direct…

• 4 min read
Direct Memory Interface , Zynq-7000' , SystemC , Virtual Platforms , linux

Verification

DAC 2012: The Top Seven Reasons for using FPGA Based Prototyping

John Blyler, Editorial Director at Extension Media , presented in our EDA360 Theatre…

• 3 min read
RPP , FPGA Based Prototyping , Custom FPGA Boards , hardware/software integration , cadence , Acceleration , debug , Functional Verification , System Design and Verification , System Development Suite , embedded software , JTAG , Emulation , virtual prototype , Software Development and Debug , xilinx , DAC 2012 , HAPS , John Blyler , Design Automation Conference , system integration , FPGA

System, PCB, & Package Design 

Shocking Rules and Material Remove ESD Risk in Allegro PCB Smartphone Designs

Static electricity can send shocks through your body. We have all experienced walking…

• 2 min read
PCB , VSD , shock , Team Allegro , electrostatic discharge , electric shock , XStatic , ESD protection , Shocking Technologies , SPB , smartphones , Allegro , ESD

Verification

DAC 2012 Video: R&D Fellow Mike Stellfox on the Emerging Bottlenecks in SoC System…

R&D Fellow Mike Stellfox leads a group of trailblazers inside Cadence. Specifically…

• less than a min read
DAC , Joe Hupcey III , interview , debug , video , SoC , Mike Stellfox , DAC 2012 , verification

Verification

DAC 2012: Enabling the Programming of an Extensible Processing Platform

We at Cadence have been writing about the virtual prototype associated with the Xilinx…

• 6 min read
DAC , Virtual System Platform , cadence , debug , Functional Verification , System Design and Verification , System Development Suite , embedded software , virtual prototype , Software Development and Debug , firmware , Performance Analysis , xilinx , DAC 2012 , Design Automation Conference , system integration

Verification

High-Level Design and Verification: How Can We Finally Move on From the Forrest Gump…

Richard Goering wrote an excellent summary of the DAC panel "High Level Synthesis…

• 3 min read
DAC , TLM , DAC panel , high-level verification , RTL , Forrest Gump , high-level design , SoC , System Design & Verification , SystemC , C-to-Silicon Compiler , high level synthesis , HLS , C++ , ESL , verification

Digital Design

EDI System’s get_metric Command Makes Metrics Reporting Quick and Easy

In this blog post I want to highlight the command get_metric that was introduced…

• 3 min read
get_metric , SoC-Encounter , cadence.com community , cadence , EDI system , EDI 11.1 , Cadence Online Support , encounter , EDI 10.1 , Digital Implementation , Encounter Digital Implementation , SoC Realization , EDI 11 , "SoC-Encounter"
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