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Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO
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Blog - Post List
Latest blogs

Verification

UVM: "Everything that Can be Invented Has Been Invented" Not True!

Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification…

• 1 min read
SystemVerilog , uvm , Functional Verification , UVM e , UVM-MS , 20nm , Low-Power , Incisive , Mixed-Signal , multi-language , Acellera VIP TSC , mixed signal , MDV , IES , VMM

Digital Design

Five-Minute Tutorial: Multiple View-Only Windows In EDI

Have you ever had a situation where you want to compare two (or more) different areas…

• 1 min read
windows , First Encounter , view-only , viewer , encounter , EDI 10.1 , Digital Implementation , five minute tutorial

Verification

Event Report: Club Formal UK – Cache Coherency, UVM for ABV, and Brainstorming with…

Right before the December holidays it was my privilege to host the first "Club Formal…

• 3 min read
uvm , Vincent Reynolds , ABV , Joerg Mueller , metric driven verification (MDV) , ABVIP , coherency , assertions , Club Formal , UK , MDV , Bob Kurshan , Assertion-based verification

System, PCB, & Package Design 

What's Good About APD’s Die Abstract Libraries? You’ll Need the 16.5 Release to See

In System in Package (SiP) 16.3, the co-design die flow introduced the distributed…

• 10 min read
PCB , IC Packaging and SiP Design , IC Packaging , packaging , PCB design" , Digital SiP design , CML , die abstracts , APD , Allegro 16.5 , IC/package co-design , Allegro Package Designer , Layout , design , "PCB design" , PCB design , die abstract compare , SPB16.5 , Librarians , library , Allegro

System, PCB, & Package Design 

What's Good About Allegro GRE Constraint Region Support? It’s in the 16.5 Release

The 16.5 Global Route Environment ( GRE ) now allows or prohibits tuning in constraint…

• 1 min read
PCB , PCB Layout and routing , constraint region , Routing , Allegro 16.5 , PCB Editor , Layout , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , GRE , Allegro

Digital Design

Five-Minute Tutorial: Avoid SI Problems With Better Pin Placement In Encounter Digital…

I know we're over halfway through January already (where does the time go?), but…

• 1 min read
assignPtnPin , SI analysis , noise analysis , encounter , pin placement , EDI 10.1 , Digital Implementation , five minute tutorial

Verification

2012 CES: Top 3 Trends Impacting EDA This Year

For years now consumer electronics have driven (nay, saved) the EDA industry. Hence…

• 4 min read
Intel , DAC , Joe Hupcey III , OLED 3D , TV , Consumer Electronics Show , Formal Analysis , CES , formal , 14nm , EDA360 , CES2012 , OLED , DVcon , apps , ARM , LG

RF Engineering

SpectreRF AppNotes and Tutorials....Still One of our Best Kept Secrets!

Some of you may remember the blog written several years ago " Shhhhh...SpectreRF…

• 3 min read
RF , RF Simulation , analog/RF , APS , HBnoise , envelope , QPSS Analysis , shooting newton , HB , Spectre RF , Spectre AppNotes , MMSIM , pnoise , phase noise , Virtuoso Spectre Simulator GXL , fast envelope , analog , ADE , RF spectre spectreRF , Virtuoso Spectre Simulator XL , Virtuoso , Spectre , RF design , harmonic balance , mixer , VCO , RF Measurement library , pss , SpectreRF tutorials , Oscillator

System, PCB, & Package Design 

What's Good About Allegro PCB Router Inset Vias? See for yourself in 16.5!

Another high density interconnect (HDI) technology that has gained popularity is…

• 1 min read
PCB , PCB Layout and routing , interconnects , inset vias , Routing , layer stacks , High Speed , Allegro 16.5 , PCB Editor , High-Density Interconnect , Layout , via , design , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , HDI , Allegro

Verification

Creating the Zynq Virtual Platform, Including Errata

Although I have never contributed any code to the Linux kernel, the headline We are…

• 5 min read
Virtual System Platform , virtual prototoypes , zynq , virtual platforms , IP-XACT , errata , embedded software , SystemC , linux , Embedded Linux , System Design and Verification

Verification

Video: Bob Kurshan, Cadence Fellow and Incisive Formal R&D Leader, talks about Formal…

Continuing the series of introducing you to the people that create the tools you…

• less than a min read
ABV , Formal Analysis , formal , video , Kurshan , cache coherency , IEV , Bob Kurshan , Formal verification , IFV , verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About Allegro Differential Pair Updates? Look to SPB16.5 and See!

The 16.5 Allegro PCB Editor release adds differential pair phase tuning as an alternative…

• 1 min read
PCB , PCB Layout and routing , Allegro 16.5 , PCB Editor , Layout , design , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , differential pairs , Differential Pair Support , Allegro

RF Engineering

Nport Application Note has been Updated and Re-Released

Happy New Year! After many requests, I set aside some time and updated the Using…

• less than a min read
nport , RF , RF Simulation , analog/RF , APS , Virtuoso Spectre , HB , Spectre RF , spectre spectreRF , MMSIM , nport settings , RF Block Simulation , analog , Virtuoso Spectre Simulator XL , spectreRF , Spectre , RF design , harmonic balance

Verification

Ubuntu Updates for 2012

I'm overdue to provide an update on how to run Virtual System Platform (VSP) and…

• 6 min read
Virtual System Platform , zynq , GDB , VSP , Incisive , Ubuntu , VirtualBox , SystemC , Virtual Platforms , System Design and Verification

Verification

TLM: The Year in Review, and Trends for 2012

2011 was my first full year in the land of Transaction-Level Modeling (TLM) design…

• 5 min read
High-Level Synthesis , ASIC , TLM , system realization , C-to-Silcon , TSMC , system design , SystemC , Hardware/software co-verification , HLS , C++ , verification

Verification

Free Formal and ABV Webinar Recordings from 2011 Online Now!

In case you missed any of the 5 free webinars Team Verify presented in 2011, you…

• 3 min read
NextOp , scoreboard , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , BugScope , Incisive , ADS , coverage driven verification (CDV) , SoC Connectivity , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification

Verification

One Oil Change and Update my Car to the Latest Software Patch, Please!

Since the IEEE Spectrum article "This Car Runs on Code" back in February 2009, my…

• 3 min read
Automotive , virtual platforms , edaForum , Infineon , V-Diagram , virtual prototypes , ECU , Bosch , System-Level Design , Freescael , Design Flows , embeded software , Engine Control Unit

Verification

Some Final Real-World Assertions for the Holidays

My last "real-world assertions" blog post seems to have tickled a bunch of people…

• 3 min read
holidays , ABV , Functional Verification , assertions , real-world assertions , Assertion-based verification

System, PCB, & Package Design 

What’s Good About OrCAD Apps? You Can Try Them for Free!

The introduction of Apps in the new Cadence OrCAD Capture Marketplace in the 16.5…

• 2 min read
PCB , Allegro Design Entry , Marketplace , Design Entry CIS , OrCAD Capture Marketplace , applications , OrCAD Capture , Capture CIS , Capture-CIS , OrCAD online store , Allegro 16.5 , Team OrCAD , OrCADapps , "PCB design" , OrCAD , Design Entry , SPB16.5 , PCB Capture , Schematic
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