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Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis
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Blog - Post List
Latest blogs

Verification

Specman 9.2 Preview: Named Constraints

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to…

• 6 min read
IntelliGen , Specman , debug , Functional Verification , e , AOP , IES-XL

Verification

DAC Best User Track: Visualizing Debugging Using Transaction Explorer in SoC System…

One of the great things about DAC is the opportunity to meet new people and find…

• 2 min read
DAC , System Design and Verification , Incisive , SoC , Marvel

Verification

Survey Results and Commentary on The XJTAG Girls at DAC 2009

In my last post, I recounted the disproportionate buzz received by the "XJTAG Girls…

• 7 min read
DAC , Functional Verification , OVM , XJTAG

System, PCB, & Package Design 

What's Good About Blogging? - The People: Readers, Posters, Cadence!

I'm taking a break this week from the technical type posts to say THANK YOU to the…

• 2 min read
IC Packaging and SiP Design , PCB design , FPGA

Verification

More Details on Post Silicon Embedded Software Verification With ISX

Please welcome back Joerg Simon and Markus Winterholer, both from the ISX team in…

• 3 min read
AXI , eVC , System Design and Verification , OVM , SoC , ISX , ARM , ESL , FPGA

Digital Design

Co-Design - Its Not Just an Exercise in Excel Any More - Learn Why at the Aug. 26…

Co-Design … some are trying to do it with spreadsheets … everyone is talking about…

• 1 min read
SoC-Encounter , Cadence SiP , Co-Design , Digital Implementation , FlipChip

Verification

Slides From DAC Virtual Platform Workshop

As a follow-up to my report on the DAC Virtual Platform Workshop I would like to…

• less than a min read
DAC , virtual platform , System Design and Verification

System, PCB, & Package Design 

What's Good About DEHDL Usability Improvements? The Secret's in the SPB16.2 Release

The Design Entry HDL (DEHDL) usability improvements are many and significant in the…

• 5 min read
SPB 16.2 , DEHDL , PCB design , Allegro

Digital Design

Useful dbGet One-Liners

We've gotten some good feedback about posts in this forum relating to dbGet and dbSet…

• 2 min read
dbGet , dbSet , Digital Implementation

System, PCB, & Package Design 

Power Issues? Manage Your IR Drop The "Advanced" Way

Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written…

• less than a min read
16.01 , PCB Layout and routing , SPB 16.2 , PCB Signal and power integrity , Allegro 16.2 , SPB16.2 , PCB design

Verification

A Quick Look Back at DAC

Well, I had good intentions of blogging from DAC , or at least summarizing my four…

• 1 min read
DAC , Verification methodology , Functional Verification , Open Verification Methodology , OVM

Analog/Custom Design

We Interrupt Your Regularly Scheduled Programming...

I thought I would have time for a regular TYDKAV (Things You Didn't Know About Virtuoso…

• 1 min read
ViVa-XL , IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Verification

A Classification of ESL - High Level Synthesis Tools

These days, there is a lot of talk of what the next design methodology for Digital…

• 3 min read
RTL , System C , ESL , System Design and Verification

Verification

Full System vs Sub-system Virtual Prototyping

There is a strong movement in the industry to move to create Virtual Prototypes of…

• 2 min read
TLM , RTL , System Design and Verification , virtual prototype

SoC and IP

Reflections on Life and Death in the Memory Sector: Spansion and Qimonda, Long on…

Hammered by market events, two significant memory suppliers suffer in Chapter 11…

• 6 min read

Verification

Intel vs ARM - Did the Embedded Systems Conference India Shed Light on the Battle…

Being a Brit, Cricket is never very far from my thoughts especially when travelling…

• 2 min read
Intel , Low Power , System Design and Verification , embedded software , ARM

Digital Design

5 Fascinating People I Met at the 2009 Design Automation Conference

As much as the Design Automation Conference (DAC) is about demonstrating solution…

• 5 min read
DAC , Digital Implementation

Verification

Post-DAC 2009 Survey on The XJTAG Girls

One non-technology item that received an extraordinary buzz at DAC 2009 were the…

• 1 min read
DAC , Functional Verification

Verification

1st Ever Virtual Platform Workshop Deemed a Success

Yesterday DAC hosted the first ever Virtual Platform Workshop , a full day dedicated…

• 2 min read
DAC 2009 , virtual platform , System Design and Verification
CDNS - Fix Layout Hompage