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Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Digital Design

MarCom 2009 - New, Exciting, Educational

As a Marketing Communications professional, I am always looking for creative ways…

• 2 min read
EDI , EDI system , encounter digital implementation system , Digital Implementation

SoC and IP

The Great Escape, Part II: How These Companies Exited the DRAM Business

Case Histories of Significant DRAM Market Withdrawals : This article continues…

• 18 min read

Verification

Inside Cadence: "Stars & Strikes" charity event

Allow me to make a brief digression from EDA technology blogging to give you all…

• 1 min read
Functional Verification , charity benefit , Stars and Strikes festival

Verification

Where's the Bridge to Cross the Great Divide?

At this year's Embedded System Conference in San Jose there was a panel with the…

• 8 min read
windows , dwarfdump , VMware , Embedded Systems Conference 2009 , ISX , Hardware/software co-verification , linux

Verification

New "E" text editor and e templates

Imagine Team Specman's surprise when we came across this article on Slashdot about…

• 1 min read
IEEE 1647 , eclipse , Specman , Functional Verification , e , AMIQ , verification , IES-XL

SoC and IP

Denali MemCon leads "Memory Week" in Silicon Valley, June 22-25

Denali MemCon 2009, scheduled for the Santa Clara Hyatt Regency on June 22-24, is…

• 1 min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Navigator Assistant

Have you ever found yourself working with a massive schematic having to constantly…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

SoC and IP

The Great Escape, Part I: How These Companies Exited the DRAM Business

Updated version to reflect correction to company naming due to errors in original…

• 8 min read

Verification

Report from CDNLive! EMEA 2009

CDNLive! in Munich had it all - stimulating customer papers, demonstrations of new…

• 1 min read
ABV , CDNLive , Functional Verification , OVM , VIP , TLA , MDV

Verification

Tech Tip: Weighting Generation of "Extreme" Values

[ Team Specman welcomes guest blogger Vitaly Lagoon, an Architect in the Generation…

• 1 min read
IntelliGen , Specman , Verification methodology , Functional Verification , Incisive , e , team specman , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Verification

Heads-up: DVClub Boston Coming Up On June 1

Back on March 19 here in Silicon Valley, verification guru Brian Bailey gave a great…

• less than a min read
events , verification strategy , Functional Verification , DVClub

SoC and IP

Memory Company Financials, 1Q09

1Q09 Better than 4Q08, but still terrible: Memory makers continued to suffer…

• 8 min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Tabs and Bookmarks

Do you remember the first time you used a browser with tabs? All of a sudden, there…

• 2 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Way Worse Than The Real Thing

This week Cadence and Virtutech announced a collaborative effort to bring together…

• 2 min read
cdnlive! emea 2009 , System Design and Verification , Incisive Enterprise Simulator , embedded software , Incisive , Coverage Driven Verification for Embedded Software , embedded SW engineer , ISX , Hardware/software co-verification , ESL , architect , Virtutech , Coverage Driven Verification

System, PCB, & Package Design 

Innovative Approach to Optimized FPGA Pin Assignment

Cadence has been a leader in silicon-package and package-board co-design for over…

• less than a min read
FPGA-PCB Co-Design , PCB design , FPGA

Verification

ESL Verification News From CDNLive! EMEA

Hello from CDNLive! EMEA in Munich. Another year has passed, and it’s time…

• less than a min read
System Design and Verification , Incisive Enterprise Simulator , Incisive , SystemC analysis , System simulation and analysis , Coverage Driven Verification for Embedded Software , SystemC , Incisive Software Extensions , Hardware/software co-verification , debugging , ESL , Virtutech , Coverage Driven Verification

Verification

System D&V at CDNLive! EMEA

CDNLive! EMEA has started today. I arrived here (Munich Germany) from SFO paying…

• 1 min read
System Design and Verification , Palladium , xtreme , Virtutech

Verification

5 min Demo: e Coding With AMIQs DVT IDE

For those of you who can't make it to the CDNLive Munich Designer Expo this week…

• less than a min read
IEEE 1647 , eclipse , Specman , CDNLive , Functional Verification , e , team specman , specman elite , AMIQ

Digital Design

Getting Started with dbSet

A while back, I posted a blog called Getting Started with dbGet . It was a brief…

• 2 min read
dbGet , dbSet , encounter , Digital Implementation
CDNS - Fix Layout Hompage