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Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis
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Blog - Post List
Latest blogs

SoC and IP

DRAMs: Historically, how bad is this downturn?

DRAMs: Another look at how bad it is: Last week, we (finally) published our summary…

• 3 min read

Verification

Software Verification or Validation With ISX?

[Please welcome Markus Winterholer to the Team ESL blog. Markus is one of the founding…

• 2 min read
validation , embedded world conference , System Design and Verification , ISX , ARM , verification

Analog/Custom Design

Virtuoso, the SATs, and The Dark Knight - Part I

You are probably wondering what Virtuoso has to do with the SATs and The Dark Knight…

• 1 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

DVCon '09 SaaS Panel Thoughts, Part 3

In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS"…

• 5 min read
SaaS , Functional Verification , Harry The ASIC Guy , DVcon , Xuropa

Analog/Custom Design

Automated Digital Block Implementation Using Virtuoso

Have you ever found yourself laying out a digital block in Virtuoso where you have…

• 2 min read
VSR , Virtuoso Custom Placer , Virtuoso , Custom IC Design , VCP

Digital Design

Great Article by Freescale: Timing Convergence Accross the Flow is "Very Important…

Having consistency and correlation in timing analysis across the design flow is …

• less than a min read
EDN , encounter , Digital Implementation , Encounter Timing System

Verification

Is Software Engineering Engineering? You Decide!

Last night when I was waiting for my daughter to finish orchestra rehearsal (she…

• 3 min read
System Design and Verification , failure tolerance , software engineering , design metrics

Analog/Custom Design

Calculating Large Signal Phase Noise Using Transient Noise Analysis

My name is Alan Whittaker and I'm in Cadence's Custom IC Proliferation Group. We…

• 2 min read
PLL , MMSIM , RF design , Circuit Design , Simulators , Custom IC Design

Digital Design

Get on Board With Bus Guides

One of the coolest new things in Encounter 8.1 is Bus Guides. I know many of you…

• 2 min read
Bus Guides , encounter , 8.1 , Digital Implementation

System, PCB, & Package Design 

What's Good About Cline Change Width in APD? It's in SPB16.2!

In IC package design, it is becoming increasingly necessary to change a cline’s width…

• 2 min read
SPB 16.2 , APD , PCB design , Cline change

Verification

Generation Action: Constraints From Above

[Welcome guest blogger Reuven Naveh of Specman R&D] What is the “constraints from…

• 6 min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Verification

Moving Low Power Chip Design up to the System Level

Anybody watching Cadence these past couple years has probably noticed how we're pretty…

• 1 min read
System Design and Verification , Palladium , incyte , C-to-Silicon Compiler

Analog/Custom Design

Moving an Ecosystem

Recently, a colleague here at Cadence created the image of an ecosystem , whose existence…

• 1 min read
ecosystem , Virtuoso , CAD , Custom IC Design

SoC and IP

Company Financials for 4Q08. Not Good

Memory Makers lose $8.8B in 4Q2008, to bring annual losses to $20B: Memory companies…

• 14 min read

Verification

Tracing TLM 2.0 Activity In An ESL Design – Part I

Many design teams that use SystemC are in various stages of evaluating TLM 2.0 –…

• 6 min read
TLM , System Design and Verification , TLM 2.0 , SystemC analysis , George Frazier , sctlmrecord , ESL

Verification

Making the Right Decisions *Before* You Start Your Project

Seems logical, but unfortunately, I run into customers today that grumble about their…

• 3 min read
InCyte IP , chipestimate , System Design and Verification , chip estimation

Verification

Connecting OVM Testbench and SystemC TLM2 IP

1. Introduction With TLM2 enabling more sophisticated SystemC IP interoperability…

• 9 min read
TLM2 IP , System Design and Verification , OVM , SystemC , testbench

Verification

C-to-Silicon Compiler Is The Only ESL Tool With ECO Capabilities

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to other…

• 1 min read
ECO , CTOS , RTL , System Design and Verification , C-to-Silicon , ESL

Verification

IMPORT Guidelines For e, Part 1

[Team Specman welcomes AE Manager Avi Behar as our newest guest blogger] Hi, my name…

• 4 min read
IntelliGen , Specman , Functional Verification , Avi Behar , OVM e , Register Package , e , OVM-e , specman elite , Aspect Oriented Programming , eRM , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL
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