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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Benedict Evans 2020: Standing on the Shoulders of Giants

For the last five or six years, Benedict Evans worked at Andreesen-Horowitz (a16z…

• 5 min read
benedict evans , Internet , mobile

Breakfast Bytes

Sunday Brunch Video for 9th February 2020

https://youtu.be/CVbxaO8cVoM Made in Steve's office (camera Steve Brown) Monday…

• less than a min read
sunday brunch

Academic Network

Certified TowerJazz-Cadence Analog Lab at KPI in Ukraine

Around one year ago TowerJazz VP, Ori Galzur, contacted us and suggested to start…

• 3 min read
Cadence Academic Network , Certified Lab , KPI , Ukraine , TowerJazz

Analog/Custom Design

Virtuosity: Blogging Journey of Virtuoso Place and Route in 2019

To support various new features and enhancements in Virtuoso Placement and Routing…

• 6 min read
tree routing , Modgen On Canvas , structured routing , ICADVM18.1 , Virtuoso Space-based Router , EXL , mesh routing , MODGEN , Automated Device-Level Placement and Routing , Virtuoso Placer , Layout EXL , trunk-to-trunk mesh , Auto P&R , Mixed-Signal , Tree Route , Layout Suite , trunk creation , Generate Trunk , Finish Trunk , EM Trunk Optimization , Custom IC Design , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

How Is the C Compiler Written in C?

Often compilers for computer programming languages are written in their own language…

• 7 min read
llvm , compiler , C++

Computational Fluid Dynamics

Boom Supersonic: Relaunching Commercial Supersonic Aircraft Travel

Authors: Michael Rybalko, Aeropropulsion Engineer, Boom Supersonic & Jean-Charles…

• 5 min read
CFD , NUMECA

Breakfast Bytes

Exadata: An Epic Journey at Oracle with Persistent Memory

A couple of weeks ago was the Persistent Memory Summit 2020. See my post Persistent…

• 5 min read
persistent memory summit , exadata , Oracle , optane , persistent memory

Verification

A Specman/e Syntax for Sublime Text 3

We're happy to have guest blogger Thorsten Dworzak, Principal Consultant at Verilab…

• 1 min read
Specman , Specman/e , Specman e , Sublime Text , specman elite

Breakfast Bytes

The Signal Integrity Story

Yesterday, I started to talk about how new technologies find their way over time…

• 5 min read
celsius , CadMOS , Signal Integrity , Sigrity , clarity

System, PCB, & Package Design 

IC Packagers: A Boundless Bounty of Bounding Shapes

How’s that for a tongue twister? Go ahead, try and say it three times fast! What…

• 4 min read
Allegro Package Designer

System, PCB, & Package Design 

BoardSurfers: High-Speed Design Signal Integrity Challenges and Solutions

Usually, people start a blog by stating something dramatic and we used to bring drama…

• 3 min read
Sigrity , Allegro PCB Editor

Breakfast Bytes

How Technologies Get into EDA

When I was last at Cadence around 2000, I ran what was then Custom IC. It was a different…

• 6 min read
sales , startups , ambit , Signal Integrity , salesforce

Breakfast Bytes

Persistent Memory at Twitter

A couple of weeks ago was the Persistent Memory Summit 2020. See my post Persistent…

• 3 min read
persistent memory summit , Oracle , optane , Twitter , persistent memory

Verification

USB3, PCIe, DisplayPort Protocol Traffic Finding its Way Through USB4 Routers

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic…

• 1 min read
Verification IP , DP , DisplayPort , USB , usb4 , PCIe , tunneling

Breakfast Bytes

Persistent Memory: We Have Cleared the Tower

Last week it was the Persistent Memory Summit 2020, which has been running annually…

• 7 min read
persistent memory summit , persistent memory , 3dxpoint

Breakfast Bytes

Quarry Bank Mill: A Technology Museum from the Industrial Revolution

A couple of years ago (and from time to time since) I wrote a series of blog posts…

• 5 min read
industrial revolution , museum

Breakfast Bytes

Sigrity Aurora: In-Design Analysis

Cadence's new Sigrity Aurora puts all the power of the Sigrity engines under the…

• 3 min read
Sigrity Aurora , Signal Integrity , Sigrity

Life at Cadence

Intelligent System Design

Electronics technology is proliferating to new, creative applications and appearing…

• 9 min read
intelligent system design

System, PCB, & Package Design 

IC Packagers: Mysteries Revealed - Why Is Flip-Chip Chip-Down the Default Library…

We’ve come to the end of my New Year’s Resolutions for 2020. Before we dive deeper…

• 4 min read
Allegro Package Designer
CDNS - Fix Layout Hompage