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Featured

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
Corporate 31 Jul 2026 • 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
Corporate 27 Jul 2026 • 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
Corporate 26 Jul 2026 • 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
Corporate 22 Jul 2026 • 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent
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Blog - Post List
Latest blogs

Breakfast Bytes

It's a SLAM Dunk Programming the Vision Q7 DSP

The Tensilica Vision Q7 DSP is the sixth-generation vision and AI DSP. It has an…

Paul McLellan 17 Apr 2020 • 5 min read
vision Q7 , embedded vision , SLAM , Tensilica

Analog/Custom Design

Start Your Engines: AMSD Flex—Take your Pick!

Introduction to AMSD Flex mode and its benefits.

Qingyu Lin 16 Apr 2020 • 2 min read
mixed signal design , AMS Designer , AMSD , AMSD Flex Mode , mixed-signal verification

Verification

Metamorphic Testing: The Future of Verification?

Curious about what’s going on behind the scenes with verification? Bernard Murphy…

XTeam 16 Apr 2020 • 1 min read
Functional Verification , Semiwiki , metamorphic testing

Digital Design

Library Characterization Tidbits: Rewind and Replay

A recap of the blogs published in the Library Characterization Tidbits blog series…

Jommy 16 Apr 2020 • 3 min read
Liberate AMS , Liberate LV , RAK , Liberate Variety , library characterization , Application Notes , Liberate MX , training bytes , Library Characterization Tidbit , Liberate Characterization Portfolio

System, PCB, & Package Design 

BoardSurfers: Five Easy Steps to Create Footprints Using Packages in Library Cre…

In my previous blog , I talked about creating a footprint using an existing template…

Sanjiv Bhatia 16 Apr 2020 • 2 min read
Library Creator , PCB Editor , 17.4-2019 , ECAD-MCAD Library Creator , PCB design

Breakfast Bytes

Bringing Clarity of Signal to High-Performance Connector Design

I recently wrote a white paper on Signal Integrity for 112G, which I'll post about…

Paul McLellan 16 Apr 2020 • 5 min read
return loss , Signal Integrity , crosstalk , clarity

Analog/Custom Design

Virtuosity: Concurrently Editing a Hierarchical Cellview

This blog discusses key features of concurrently editing a hierarchical cellview…

Sucharita 15 Apr 2020 • 2 min read
concurrent edit hierarchical subcell , concurrent layout editing , ICADVM18.1 , concurrent editing , CLE , concurrent hierarchical editing , Custom IC Design , Virtuoso Layout Suite , Custom IC , Layout Editing

Breakfast Bytes

HiFi DSPs - Not Just for Music Anymore

When the Tensilica HiFi DSP family was first created, the focus was all on low-power…

Paul McLellan 15 Apr 2020 • 4 min read
hifi 5 , Audi , HiFi , Tensilica , tensorflow lite

Whiteboard Wednesdays

Whiteboard Wednesdays - TensorFlow to RTL with High-Level Synthesis

In this week’s Whiteboard Wednesdays video, Dave Apte explains the flow from a TensorFlow…

References4U 14 Apr 2020 • less than a min read
High-Level Synthesis , Whiteboard Wednesdays , TensorFlow , Stratus

System, PCB, & Package Design 

IC Packagers: Time-Saving Alternatives to Show Element

In the Allegro back-end layout products like Allegro Package Designer Plus, it would…

Tyler 14 Apr 2020 • 6 min read
Allegro Package Designer , Allegro PCB Editor

Breakfast Bytes

The Furthest Man Has Been from Earth

What is the furthest that man has been from Earth? And who? If I tell you that today…

Paul McLellan 14 Apr 2020 • 4 min read
Apollo , space

Analog/Custom Design

Virtuoso Meets Maxwell: Keeping Things Simple in the Virtuoso RF Solution

We have all heard the sayings “Less is more” and “Keep it simple”. Electromagnetic…

kfullerton 13 Apr 2020 • 5 min read
EM Analysis , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic analysis , RF design , Custom IC Design , Virtuoso Layout Suite

Breakfast Bytes

John Park Webinar: Is It the Age of the Chiplet?

I first started paying attention to 3D packaging many years ago. Every year there…

Paul McLellan 13 Apr 2020 • 5 min read
FOWLP , chiplets , 3D IC , more than Moore , interposer

定制IC芯片设计

Virtuosity:回顾2019年Virtuoso ADE Product Suite 及 Virtuoso Visualization and Analys…

对于 Virtuoso®ADE Product Suite 和 Virtuoso® Visualization and Analysis 而言,2019 年是非常重要的一年…

shubhangi upadhyay 13 Apr 2020 • 2 min read
Chinese blog , Cadence blogs , ICADVM18.1 , ADE Explorer , virtuoso visualization and analysis , Virtuosity , Virtuoso Video Diary , Custom IC Design , ADE Verifier , IC6.1.8 , ADE Assembler

Breakfast Bytes

Sunday Brunch Video for 12th April 2020

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: From Castles…

Paul McLellan 12 Apr 2020 • less than a min read
sunday brunch

PCB、IC封装:设计与仿真分析

极致PCB设计全流程 I 基础二:DFx规则设定

当布线过程中或者布线结束时,发现器件布局不合理,我们将进行繁琐的调整工作。对于复杂PCB,这个调整可能会占用我们整个上午的时间,甚至更久。 如果设计者在布局开始时…

SDA China 10 Apr 2020 • less than a min read
PCB , Chinese blog , training , webinar , PCB设计 , 中文 , 直播网课 , online training , Allegro , 专家培训

Digital Design

Joules – Power Exploration Capabilities

Several tools can generate power reports based on libraries & stimulus. The issue…

Neha Joshi 10 Apr 2020 • 1 min read
Low Power , Joules , Logic Design , Power Analysis

Digital Design

Exploring Genus-Joules Integration is just a click away!!

Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize…

Neha Joshi 10 Apr 2020 • less than a min read
Low Power , Genus , Joules , Logic Design , Power Analysis

Breakfast Bytes

Designing Chips for Hyperscale Data Centers: Tools

Yesterday's post, Designing Chips for Hyperscale Data Centers: IP , covered the high…

Paul McLellan 10 Apr 2020 • 5 min read
cloud , cadence cloud , datacenter
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