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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Breakfast Bytes

What's For Breakfast? Video Preview October 30th to November 3rd 2017

https://youtu.be/JQVYmENG0gw Coming from the Cadence booth at Arm TechCon …

• less than a min read
ARM Techcon , Rutenbar , Cadence Academic Network , scaling , introduction to vlsi systems , intern , mead and conway , kahng , Kaufman Award , esd alliance

Analog/Custom Design

Virtuosity: Read Mode Done Right

Because of the ease with which you can set up complex sweep, corner and Monte Carlo…

• 4 min read
ADE Explorer , Custom IC Design. Read only , ADE , Analog Design Environment , ADE Assembler

Breakfast Bytes

Why Was Arm Successful in Mobile?

I think that Arm was successful in mobile (and subsequently in other markets) due…

• 5 min read
mobile , Silicon Valley , ARM , Breakfast Bytes

System, PCB, & Package Design 

Signal Integrity Methodology for Multi-Gigabit Serial Link Interfaces (1 of 8)

As data rates for serial link interfaces such as PCI Express® (PCIe®) Gen 4 move…

• 6 min read
Serial link analysis , SI , Multi-Gigabit , IBIS-AMI , PCIe , Signal Integrity , SerDes , Sigrity

The India Circuit

Opportunities in India for IoT

This week we return to the Internet of Things (IoT). My previous blogs on the subject…

• 3 min read
Government of India , CDNLive India , digital india , smart cities , IoT , IT services , Internet of Things

Breakfast Bytes

Mike Muller Gets Emotional at Arm TechCon

As usual, Arm TechCon opened with a keynote by Mike Muller, Arm's CTO. His son is…

• 6 min read
security , IoT , Mike Muller , ARM , Breakfast Bytes , Techcon

System, PCB, & Package Design 

Customer Support Recommends –Team Design in DE-HDL 17.2

Accelerating product time to market, achieving significantly higher productivity…

• 2 min read
PCB , Rapid Adoption Kit , RAK , Support , Team design

Whiteboard Wednesdays

Whiteboard Wednesdays - Automotive Memory Technologies and Trends: Technology Im…

In this week's Whiteboard Wednesdays video, the last of a three part series, Scott…

• less than a min read
Automotive , memory protocols , Whiteboard Wednesdays , Memory , NAND flash , automotive electronics , memory IP , DRAM , memory models

Breakfast Bytes

Xcelium Simulation on Arm Servers

Paul Otellini RIP Paul Otellini was CEO of Intel from 2005-2013. He died in his…

• 4 min read
ARMv8 , Intel , x86 , cloud , mobile , ARM , microprocessor , datacenter , Breakfast Bytes

Analog/Custom Design

The Art of Analog Design Part 6: Response to Frank’s Question to Part 4

In the comments to blog #4, Frank Wiedmann asked about the correlation between the…

• 3 min read
spectre aps , Virtuoso Variation Option , ADE Explorer , mismatch analysis , Analog Simulation , Monte Carlo analysis , DC Mismatch , Custom IC Design

Breakfast Bytes

Putting the Bad Guys in an Arm Lock

This morning Arm announced their Platform Security Architecture (PSA), a new way…

• 6 min read
security , ARM Techcon , mirai , platform security architecture , psa , ARM , Breakfast Bytes , Techcon

Breakfast Bytes

Education, Occupation, and You: Vishal Kapoor at SJSU

Earlier this week, Jim Hogan hosted the next evening at San Jose State University…

• 8 min read
san jose state university , vishal kapoor , san jose state , cognitive science , cognitive era , sjsu , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview October 23rd to 27th 2017

https://youtu.be/-9hc6xBOPFw Coming from SJSU Theater (camera Sean) Monday…

• less than a min read
ARM Techcon , formal , Arteris , mobile , ARM , Formal verification

Breakfast Bytes

Mark Papermaster: Moore's Law Plus

Recently, I wrote about Robert Lang's presentation on Computational Origami . He…

• 4 min read
epyc , has , chiplets , rocm , AMD , 3DIC , 2.5D IC , Breakfast Bytes

Breakfast Bytes

How to Build and Connect a Trillion Things: Arm TechCon Preview

Rob Aitken is digging a bit deeper into what it would really take to connect a trillion…

• 7 min read
security , ARM Techcon , trust , IoT , Internet of Things , ARM , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - What's Driving Automotive Memory Trends and Technologies…

In this week's Whiteboard Wednesdays, the second in a three-part series, Scott Jacobson…

• less than a min read
Automotive , Whiteboard Wednesdays , automotive electronics , ADAS , memory models

The India Circuit

Have an e-Cracker of a Diwali!

Diwali is finally here! One of India’s most favorite festivals, it is celebrated…

• 2 min read
e-cracker , firecrackers , Cadence India , Diwali , e-pataka

Verification

Munich October 18—Come See SystemC Evolution Day!

Sorry, you missed Oktoberfest (which is mostly in September anyway). But come to…

• 2 min read
Munich , Functional Verification , Accellera , SystemC , event

Breakfast Bytes

The Empire Long Divided Must Unite

Chinese children are familiar with the opening lines of Romance of the Three Kingdoms…

• 6 min read
organization , functional organization , corporate cad cycle , CEO , three envelopes , Breakfast Bytes
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