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DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

Veena Parthan
• 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

Breakfast Bytes

What's For Breakfast? Video Preview January 8th to 12th 2018

https://youtu.be/txCnT3N4OSY Coming from Executive Briefing Center (camera Sean…

• less than a min read
Consumer Electronics Show , CES , CES2018 , semi , Virtuoso , ARM

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (3 of 8)

IBIS-AMI Modeling With initial PCB trace and via models in place for our hypothetical…

• 2 min read
Serial link analysis , SI , Multi-Gigabit , IBIS-AMI , PCIe , Signal Integrity , SerDes , Sigrity

Breakfast Bytes

Gary Patton on GF, IBM, 7nm, EUV, and More

At IEDM in December, I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to discuss…

• 8 min read
fab8 , 7lp , 12fdx , gf , gary patton , malta , 12lp , GlobalFoundries , 7nm

The India Circuit

Face Recognition and Hackathon: An Unlikely and Innovative Combination

Happy New Year! While most other folks are just easing back to work, those of us…

• 4 min read
VLSI & Embedded Systems Design Conference , Tensilica , Tensilica Xtensa , neural networks , CNN , face recognition

Breakfast Bytes

Intel 10nm

At IEDM last month, Intel announced details of their 10nm process. Later the same…

• 5 min read
Intel , coag , FinFET , 10nm , Breakfast Bytes

Breakfast Bytes

Frankenstein

"Hail to thee, blithe spirit! Bird thou never wert"...and Frankenstein. What do these…

• 3 min read

Breakfast Bytes

What's For Breakfast? Video Preview January 1st to 5th 2018

https://youtu.be/Xja6H1meqac Coming from Yosemite National Park (camera Carey…

• less than a min read
Intel , ces 2017 , Consumer Electronics Show , CES , GlobalFoundries , 7nm , 10nm

Breakfast Bytes

Why Don't Planes Obey Moore's Law?

In my post about Silexica ( Silexica: Mastering Multicore ) I said that I like to…

• 9 min read
great flight diagram , aeronautics , tennekes , flight , simple science of flight

Analog/Custom Design

Virtuosity: From Hatchlings to Fledglings to a Flock of Birds Blogging Together

“The reason birds can fly and we can't is simply because they have perfect faith…

• 2 min read
Cadence blogs , Virtuoso , RF design , Virtuosity , Virtuoso Video Diary , CPG Technical Communications Engineering

Breakfast Bytes

Blue LEDs, Nobel Prizes, and IEDM Keynote

At IEDM last week, for the first time, there was a second plenary session (awards…

• 6 min read
gallium nitride , nobel prize , Wally Rhines , LED , blue led , gan , IEDM

Breakfast Bytes

Ploughing 1 TB of RAM with Twenty x86 Oxen and 10,000 RISC-V Chickens

OK, that wins the prize for best title of a presentation in the recent RISC-V workshop…

• 11 min read
risc-v , celerity , boom , picochip , risc-v foundation , esperanto , sifive

Whiteboard Wednesdays

Whiteboard Wednesdays - What to expect from TLM 2.0 Models for Memory Subsystems…

In this week's Whiteboard Wednesday, Vivek Nandakumar explains the behavioral differences…

• less than a min read
Whiteboard Wednesdays , Memory , TLM 2.0

Breakfast Bytes

RISC-V Workshop, Milpitas

The latest semi-annual RISC-V workshop took place the week after Thanksgiving. The…

• 8 min read
Western Digital , risc-v , celerity , boom , picochip , risc-v foundation , esperanto , 16nm , 7nm

Learning and Support

What's New in Cadence Help 3.0?

I am sure you would agree when I say that a help tool is the one utility without…

• 3 min read
Self-Help , Cadence Help , Help resource , Cadence support

Breakfast Bytes

COTS? Commercial Products in US Government Electronics

COTS is government jargon for Commercial Off-The-Shelf. This means the government…

• 8 min read
us government , minsec , department of defense

The India Circuit

Four Exciting Examples of Modern AI from NVIDIA

A few months ago, we had the honor of having Vishal Dhupar, Managing Director of…

• 4 min read
artificial intelligence , deep learning , NVIDIA , machine learning , AI

Analog/Custom Design

Virtuosity: SKILLful Virtuoso Visualization and Analysis

If you’re a SKILL enthusiast, you’ll be happy to know that the latest IC6.1.7 ISR…

• 4 min read
Analog Design Environment , ViVa-XL , custom/analog , Analog Simulation , SKILL for the Skilled , ADE , Virtuoso , ViVA , Virtuosity , Custom IC Design , SKILL , Cusstom IC Design

Breakfast Bytes

IEDM 2017

The start of December means it is the International Electron Devices Meeting in San…

• 6 min read
Intel , copper beol , 3D IC , AMD , georgia tech , Samsung , TSMC , fanout wafer packaging , GlobalFoundries

Analog/Custom Design

Virtuosity: Can I Graphically Edit Width Spacing Patterns?

We have enhanced the editing modes available for WSPs. In addition to the text-based…

• 1 min read
Routing , Advanced Node , width spacing patterns , Layout , Virtuoso , Virtuosity , Custom IC Design
CDNS - Fix Layout Hompage