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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Why is Power Integrity Hot (or is it Cool)?

When designing next-generation products, the common theme is "faster, smaller, cheaper…

• 2 min read
Power Integrity , electrical-thermal co-simulation , Sigrity , thermal

Breakfast Bytes

Do You Know What Stingray Is?

If you are my age and grew up in Britain, then Stingray was one of the fore-runners…

• 4 min read
imsi catcher , law enforcement , mobile , stingray

Breakfast Bytes

Litho Physical Analyzer PLUS

Next week it is the SPIE Advanced Lithography Conference (and DVCon, and MWC in Barcelona…

• 3 min read
asml , imec , Virtuoso , Innovus , LPA , lpa plus

Whiteboard Wednesdays

Whiteboard Wednesdays - Simplifying SoC Verification with Interconnect Workbench

In this week’s Whiteboard Wednesdays video, Shin Chan Kang explains how the Cadence…

• less than a min read
Verification IP , Interconnect Workbench , uvm , Whiteboard Wednesdays , VIP , SoC , Shin Chan Kang

Digital Design

Making Hardware Design Great Again in 2017 - Part Deux

In part one of this series, we talked about the role of the hardware designer , specifically…

• 5 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS

Breakfast Bytes

What's For Breakfast? Video Preview March 6th to 10th 2017

https://youtu.be/ygs0CEZXtAI Coming from Mobile World Congress, Barcelona,…

• less than a min read
gsma , Mobile World Congress , silicon photonics , netflix , mobile carriers , mobile , irps , GlobalFoundries , reliability , formula e

Breakfast Bytes

Protium: Next Generation FPGA Prototyping

FPGA prototyping is a very attractive tool for some aspects of verification. Apart…

• 5 min read
palladium z1 , Protium , FPGA prototyping , xilinx , protium s1 , FPGA

Breakfast Bytes

Xcelium: Parallel Simulation for the Next Decade

This morning, Cadence announced two new products in the verification space: Xcelium…

• 4 min read
SystemVerilog , RTL simulation , Verilog , rocketsim , xcelium , simulation

Academic Network

2nd Tensilica Day in Hanover: AR, IoT, Automotive. Pick What You Like

After the successful Tensilica Day at Hanover University last year ( presentations…

• 2 min read
hololens , Cadence Academic Network , IoT , Espressif , Tensilica , ADAS

Analog/Custom Design

Virtuoso Video Diary: Why Should you Switch to the Expression Builder for Creating…

Here’s how you can create expressions using the Expression Builder in 4 easy steps…

• 6 min read
Analog Design Environment , ADE Explorer , Analog Simulation , expressions , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design , calculator , ADE Assembler

Breakfast Bytes

DesignCon and Target Impedance

I was DesignCon recently. It is a bit of a weird conference, since it covers a wide…

• 3 min read

Breakfast Bytes

Mobile World Congress: Hololens and More

From February 27th to March 2nd it is Mobile World Congress (MWC) in Barcelona, Spain…

• 2 min read
barcelona , Mobile World Congress , Tensilica , #mwc17

Breakfast Bytes

What's For Breakfast? Video Preview February 26th to March 2nd 2017

https://youtu.be/RIkl4O5Q-V4 Coming from inside the Intel Museum, Santa Clara…

• less than a min read
Intel , spie advanced lithography , law enforcement , DVcon , mobile , privacy , intel investor day , stingray

SoC and IP

Three New Memory Trends in Enterprise Data Centers

You might have seen the graph below about the increase in monthly internet traffic…

• 5 min read
Design IP , Memory , DDR4 , flash , memory IP , DDR , memories

Digital Design

Making Hardware Design Great Again in 2017

Ok, I admit it… that title is a blatant attempt to grab your attention. But it should…

• 4 min read
High-Level Synthesis , digital implementation , Digital Implementation , HLS

Breakfast Bytes

Putting a Rocket Under Incisive

When Cadence first acquired RocketSim, I wrote a post, Omnia Simulation in Tres Partes…

• 3 min read
SystemVerilog , Incisive , Verilog , rocketick , rocketsim , simulation

Whiteboard Wednesdays

Whiteboard Wednesdays - Memory Models Runtime Control

In this week's Whiteboard Wednesdays video, Dharini SubashChandran explains how to…

• less than a min read
runtime , Whiteboard Wednesdays , IP , memory IP , Dharini SubashChandran

Breakfast Bytes

Cat-NB1 and HaLow Wireless Links Powered by Tensilica Fusion F1

A generic Internet of Things (IoT) device consists of some sensors, some computations…

• 4 min read
tensilica fusion f1 , tensilica fusion , tensilica f1 , Tensilica , narrowband , nb-iot , commsolid

Verification

What Sort of Bugs Does Portable Stimulus Find?

In a recent blog post , we discussed some general concepts of bugs, problems, issues…

• 3 min read
hardware-software co-verification , uvm , Low Power , pswg , debug , Functional Verification , System Design and Verification , embedded software , Emulation , Accellera , Hardware/software co-verification , debugging , portable stimulus , interrupts
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