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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Digital Design

Faster and Smarter

At the Cadence VIP dinner at Korea CDNLive last month, Paul Cunningham spoke about…

FormerMember • 1 min read
cdnlive korea , deep learning , CDNLive , machine learning , digital , signoff

Analog/Custom Design

Virtuosity: Power Filtering!

Finally, we have filters in the Corners Setup form, Results tab, Outputs tab, Data…

• 2 min read
Analog Design Environment , ADE Explorer , Filtering , ADE , Virtuoso Analog Design Environment , Analog Design Environment , ADE Assembler

Breakfast Bytes

EDPS: The Remains of the Day

EDPS is the Electronic Design Process Symposium, historically held in Monterey, but…

• 12 min read
deep learning , electronic design process symposium , EDPS , Test , machine learning , design , Breakfast Bytes

System, PCB, & Package Design 

CDNLive China: Interviewing with Allegro R&D VP Saugat Sen

Recently, CDNLive China was held in Shanghai. What are the highlights of PCB Track…

• 2 min read
CDNLive , cdnlive china , PCB design , Allegro

Breakfast Bytes

CDNLive Taiwan Automotive Panel

At CDNLive in Taiwan in August, there was a record number of attendees, with about…

• 8 min read
Automotive , hsinchu , CDNLive , TSMC , Renesas , cdnlive taiwan , phison , ADAS , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Complexity Optimization of Convolutional Neural Networks…

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, discusses…

• less than a min read
Whiteboard Wednesdays , convolutional neural networks , CNN

Breakfast Bytes

What's For Breakfast? Video Preview October 9th to 13th 2017

https://youtu.be/SVVE2vM4L6U Coming from Alum Rock Park (camera Carey Guo)…

• less than a min read
conformal , China , Chris Rowen , LEC , linley group , semi , grace hopper , vision

The India Circuit

IoT In Smart Factories, Healthcare, Agriculture and More

Last week’s blog ended with some of the IOT trends that Somshubhro Pal Choudhury…

• 4 min read
Automotive , IoT , smart factories , vertical markets , Internet of Things , robotics , ADAS , drones , healthcare , Smart Home

Breakfast Bytes

Scaling Embedded Inference Performance for Deep Learning

Tomorrow it is the Linley Microprocessor Conference and Pulin Desai of Cadence is…

• 6 min read
Vision P5 , deep learning , deeplearningmachinelearning , inference , convolutional neural network , training , Tensilica , CNN , neural network , Breakfast Bytes

Breakfast Bytes

AMD's Early Experience with Portable Stimulus

PSS is the Accellera Portable Stimulus Standard. Or I should say proposed standard…

• 4 min read
ryzen , AMD , Perspec , pss , portable stimulus , Breakfast Bytes

Learning and Support

Product Page: All Product-Related Information and Knowledge Content in One Place

In the past, some of you have expressed the desire to have all the information and…

• 1 min read
product , suppport , support resources

Verification

When Arm meets Intel – Overcoming the Challenges of Merging Architectures on an SoC…

As the stakes for winning server segment market share grow ever higher an increasing…

• 2 min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Breakfast Bytes

Building a Business Model

You know how you sometimes say "the other day" as if it was last week, or maybe the…

• 8 min read
business model , pitch deck , garage ventures , reichert , Breakfast Bytes , venture capital

Breakfast Bytes

SJSU School of Cognitive Science

Jim Hogan is a graduate of San Jose State University. Despite the prestige of Stanford…

• 7 min read
san jose state university , san jose state , cognitive science , cognitive era , sjsu , Breakfast Bytes

The India Circuit

IOT: Are We There Yet?

One of the invited talks that we had at CDNLive was by Somshubhro Pal Choudhury,…

• 4 min read
hype cycle , CDNLive India , IoT , IOT stack , IOT trends , Internet of Things

Breakfast Bytes

Machine Learning for Higher Performance Machine Learning

The second day keynote at the recent (well, over a month ago, there's been lots to…

• 6 min read
tpu , Jeff Dean , google , hotchips , TensorFlow , machine learning , NAE goals , machinelearningdeeplearning , Tensor Processing Unit , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Complexity Optimization of Convolutional Neural Networks…

In this week’s Whiteboard Wednesdays, Raul Casas, systems architect IP group, talks…

• less than a min read
Whiteboard Wednesdays , machine learning , convolutional neural networks , CNN

Breakfast Bytes

What's For Breakfast? Video Preview October 2nd to 6th 2017

https://youtu.be/uT2vXsXHV6s Coming from my car (camera Sean) Monday: AMD…

• less than a min read
deep learning , tensiilica , formal , EDPS , sjsu , portabe stimulus standard , Jim Hogan , pss , Formal verification

Verification

Single Core vs. Multi Core: Simulation in Stereo

Latency simulations are the sworn enemy of the verification schedule. A handful of…

• 2 min read
Single-Core , Functional Verification , Multi-Core , xcelium , simulation
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