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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Breakfast Bytes

CDNLive EMEA Zwei

This is the second post about CDNLive EMEA in Munich. Here is the first . If the…

• 9 min read
CDNLive , virtual platform , CDNLive EMEA , Bosch , CDNLive Munich , OrCAD , ARM , arrow , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview May 22nd to 26th 2017

https://youtu.be/Frsw0YkUF5M Coming from Marienplatz, Munich, Germany (camera…

• less than a min read
open source silicon , computer architecture , risc-v , Heart of Technology , Denali Party , isa , Denali , open source , instruction set architecture

Whiteboard Wednesdays

Whiteboard Wednesdays – Tensilica Fusion G6 DSP Takes on Automotive ADAS Radar A…

In this week's Whiteboard Wednesdays video, Pushkar Patwardhan gives an overview…

• less than a min read
DSP , Whiteboard Wednesdays , fusion G6 , Fusion G3 , radar , Tensilica , Fusion DSP Family

Breakfast Bytes

CDNLive EMEA Eins

Every CDNLive has a little bit of a different structure. At CDNLive EMEA in Munich…

• 7 min read
High-Level Synthesis , Automotive , Tom Beckley , CDNLive , CDNLive EMEA , iN7 , JasperGold , HLS , Breakfast Bytes

RF Engineering

7 Habits of Highly Successful S-Parameters: How to Simulate Those Pesky S-Parameters…

Hello Spectre Users, Simulating S-parameters in a time domain (transient, periodic…

• less than a min read
S-parameter , Spectre RF , Spectre , International Microwave Symposium

Breakfast Bytes

JasperGold: Stepping up to RTL Signoff

When I was on my last tour of duty at Cadence in the early 2000s, we had a late afternoon…

• 7 min read
Intel , Jasper , JasperGold , Formal verification

Breakfast Bytes

The New Tensilica Fusion G6 DSP

Only last week, in Are General-Purpose Microprocessors Over? I wrote about how general…

• 4 min read
fusion G6 , Tensilica , Breakfast Bytes , digital signal processor

Computational Fluid Dynamics

Fluid Dynamics Simulation of a Generic Gas Turbine Combustor

This case study on combustion and radiative heat transfer in a generic gas turbine…

• less than a min read

Breakfast Bytes

FD-SOI State of the Union: There's Supply—Is There Demand?

I went to the annual SOI Silicon Valley Symposium recently. As last year, they had…

• 11 min read
dreamchip , China , NXP , 22fdx , 12fdx , Samsung , handel jones , GlobalFoundries , ARM , ibs , Breakfast Bytes , FD-SOI

Analog/Custom Design

Virtuosity: What's New in analogLib

It's been a while since analogLib was updated, so we decided to pay some attention…

• 4 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , ADE , Virtuoso , Analog Design Environment , Schematic Editor , Virtuosity , Custom IC Design , Schematic , ADE Assembler

Breakfast Bytes

RISC-V 6th Workshop 上海

The 6th RISC-V workshop was held in early May. It was the first one in Asia, at Shanghai…

• 11 min read
computer architecture , risc-v , risc-v foundation , dave patterson

Breakfast Bytes

What's For Breakfast? Video Preview May 15th to 19th 2017

https://youtu.be/WTQhUyl2BBE Coming from Jing'an Park, Shanghai, China (camera…

• less than a min read
Automotive , dreamchip , CDNLive , CDNLive Munich , Tensilica , software development

Breakfast Bytes

Are General-Purpose Microprocessors Over?

There is apparently a rule of thumb among journalists that when the headline of an…

• 8 min read
Intel , risc-v , processor , MIPS , Tensilica , RISC , ARM , microprocessor , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - CNN Challenges: Compute Requirement

In this week's Whiteboard Wednesdays video, Megha Daga takes a deep dive into compute…

• less than a min read
Whiteboard Wednesdays , convolutional neural networks

Breakfast Bytes

Soft Error Rates in Satellites and Cars

Space turns out to be an interesting area for semiconductors, especially looking…

• 8 min read
Automotive , st microoelectronics , ser , soft error rate , cubesat , see , single event effect , seu , space , Breakfast Bytes , satellite

Breakfast Bytes

NASA: "Never Have Another Accident Due to Our Organizational Flaws"

The keynote at the IRPS reliability conference I attended was by Nancy Currie-Gregg…

• 7 min read
space shuttle , NASA , Breakfast Bytes , reliability

Breakfast Bytes

TSMC @ N7 with Cadence

One presentation at the recent CDNLive Silicon Valley was about using Cadence tools…

• 4 min read
Genus , Tempus , TSMC , n7 , Innovus , Quantus , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: How Can I Plot or Evaluate with the New Expression Builder…

Indeed, the new Expression Builder has made expression creation much easier, but…

• 3 min read
Analog Design Environment , evaluateADE Explorer , Analog Simulation , plot , expressions , analog , Mixed-Signal , Expression Builder , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design , calculator

Breakfast Bytes

UVM Is Now IEEE 1800.2 and There's a Ten-Year Story to That

UVM, the Universal Verification Methodology, just became IEEE 1800.2-2017. I wondered…

• 6 min read
SystemVerilog , Superlog , ieee 1800.2 , uvm , Accellera , Breakfast Bytes
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