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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Breakfast Bytes

TSMC Process Roadmap Update

This Wednesday was TSMC's OIP Ecosystem Forum, one of two major events that TSMC…

• 5 min read
22_ULP , 22_ULL , 7nm+ , 12FFC , TSMC , 16FFC , 28HPC+ , 7nm , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview September 18th to 22nd 2017

https://youtu.be/mrUIXwMuNy8 Coming from TSMC OIP Symposium, Santa Clara (camera…

• less than a min read
legato , CDNLive , hong kong , neural nets , India , Singapore

Breakfast Bytes

Why Are Design Tools So Bad? Or Are They?

In a recent feature article at Electronic Engineering Journal, Kevin Morris asks…

• 6 min read
electronic engineering journal , bugs , EDA , design tools

The India Circuit

CDNLive India Keynote: Qualcomm On 5G And More

CDNLive India concluded last Friday and what an event it was! With 87 paper presentations…

• 4 min read
5G , artificial intelligence , CDNLive India , CDNLive , IoT , machine learning , Qualcomm , mobile , 7nm

Breakfast Bytes

New Cadence Support of TSMC 7nm, 7nm+, and 12FFC

A quick guide to TSMC processes. There is a 10nm process but very little development…

• 4 min read
OIP , 7nm+ , 12FFC , TSMC , DDR , 7nm , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Benchmarking Deep Learning Platforms: The Results

In this week's Whiteboard Wednesdays video, Mengjun Leng follows up on last week…

• less than a min read
Whiteboard Wednesdays , deep learning

SoC and IP

Cadence IP Is Great for Automotive

If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision…

• less than a min read
USB 3.0 , Design IP , DDR4 , LPDDR4 , PCI Express 3.0 , LPDDR , IP blocks , PCIe Gen4 , MIPI , DisplayPort , Automotive Ethernet , USB , memory IP , Ethernet , PCIe , 16nm , PCIe Gen3 , imaging , Ethernet PHYs , PCI

Verification

How to Get to a Trillion Devices in the Internet of Things in 2035

Next month at Arm TechCon, one of the key discussion topics with be the internet…

• 4 min read
prototyping , cadence , palladium z1 , IoT , Socrates , Emulation , Internet of Things , ARM , protium s1 , verification

Analog/Custom Design

Virtuosity: Driving Along a Longer Route May Take You Home Sooner!

On my way back home every day, I need to make a decision — should I drive less, or…

• 4 min read
library manager , Virtuoso , Virtuosity , physConfig , CPH , copy library , Custom IC

Breakfast Bytes

Automotive IP Family for TSMC 16FFC

At the semiconductor level, automotive poses huge challenges due to an experience…

• 3 min read
OIP , tsmc 9000A , TSMC , renasas , Ethernet , PCIe , semiconductor IP , DDR , Breakfast Bytes

Digital Design

Why Pegasus Is the Biggest Breakthrough in SoC Physical Verification in 20 Years…

These days, DRC rule deck availability for the market tools is not a major issue…

• 3 min read
Physical verification , massively scalable , pegasus , DRC , Cloud ready

Breakfast Bytes

Xilinx/Arm/Cadence/TSMC Announce World's First 7nm CCIX Silicon Demonstrator; and…

"It takes a village to raise a child," as the African proverb says. It seems to take…

• 3 min read
ARM Techcon , cadence , ccix , TSMC , accelerator , xilinx , 7nm , Breakfast Bytes , FPGA

Breakfast Bytes

CDNLive Boston Keynotes

There were three keynotes to kick off CDNLive Boston. Tom Beckley gave the Cadence…

• 8 min read
Automotive , Tom Beckley , Protium , Palladium , silicon photonics , ADAS , Medtronic , Breakfast Bytes

Breakfast Bytes

Neural Engineering System Design

At HOTCHIPS 2017, we had a special break so we could watch the eclipse. Of course…

• 4 min read
brain encoding , neuron , hotchips , Breakfast Bytes , cortical modem

Analog/Custom Design

Virtuosity: Saving, Loading and Sharing ADE Annotation Settings

The whole ADE annotation flow was overhauled way back in IC6.1.6 but at that time…

• 4 min read
ADE Explorer , Annotation Settings , ADE Annotations , ADE , Analog Design Environment , Schematic Editor , Virtuosity , Schematic , ADE Assembler , annotation setup

Breakfast Bytes

What's For Breakfast? Video Preview September 11th to 15th 2017

https://youtu.be/ljGLKZ0gz8c Coming from Singapore Botanic Garden (camera Page…

• less than a min read
OIP , ccix , TSMC

Breakfast Bytes

Quantus FS Field Solver for the FinFET Era

For any parasitic extraction tool, there is always a tradeoff between performance…

• 4 min read
Extraction , netlist , field solver , quantus fs , Breakfast Bytes , foundry

Verification

How To Create L3 Cache Command Overflow Stress Test in Less Than 2 Days

One category of difficult SoC tests to create are stress tests, to validate the limits…

• 4 min read
SoC verification , perspec system verifier , Accellera , pss , portable stimulus

Whiteboard Wednesdays

Whiteboard Wednesdays - Benchmarking Deep Learning Platforms

In this week's Whiteboard Wednesdays episode, Mengjun Leng investigates different…

• less than a min read
Whiteboard Wednesdays , deep learning
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