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Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Breakfast Bytes

What's For Breakfast? Video Preview May 8th to 12th 2017

https://youtu.be/sIFo4JKjVxw Coming from NASA Ames Research Center, Sunnyvale…

• less than a min read
space shuttle , risc-v , NXP , ser , 22fdx , soft error rate , 12fdx , Samsung , single event upset , Tensilica , single event effect , ST Microelectronics , GlobalFoundries , ARM , microprocessor , NASA , reliability , FD-SOI

Breakfast Bytes

Bayern München Will Not Be at CDNLive Munich: Here's What They Will Miss

Yes, it's true. After attending CDNLive EMEA for the last couple of years, Bayern…

• 3 min read
Automotive , NXP , Munich , CDNLive , CDNLive EMEA , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays – Introduction to Cadence Tensilica Vision C5 DSP

In this week's Whiteboard Wednesdays video, Pulin Desai describes the main features…

• less than a min read
Whiteboard Wednesdays , Vision DSP , convolutional neural networks , CNN

Breakfast Bytes

Test Flying Pegasus

Scott Barric of MicroSemi is one of the people who have been using the pre-release…

• 5 min read
Physical verification , pegasus , DRC , cloud , microsemi , design rule check , PVS , Breakfast Bytes , cloud computing

Digital Design

Designing for Low Power… Begin at the Beginning

So you have your RTL written, and it’s time to optimize to reduce power. If that…

• 3 min read
Low Power , high level synthesis , power , HLS

Analog/Custom Design

Virtuosity: The Reboot

It’s been quite a while since I wrote about “Things I Learned by Browsing Cadence…

• 2 min read
Analog Design Environment , ADE GXL , ADE Explorer , Rapid Adoption Kit , Analog Simulation , ADE XL , ADE , ADE-GXL , Analog Design Environment , ADE-XL , Virtuosity , Custom IC Design , ADE Assembler

Breakfast Bytes

Vision C5 DSP for Standalone Neural Network Processing

I pointed out recently that although La La Land is a romance, the movie opens with…

• 6 min read
DSP , Vision C5 , embedded vision , Embedded Vision Alliance , Tensilica , semiconductor IP , embedded vision conference , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 1

In this week's Whiteboard Wednesdays video, Tom Hackett traces the evolution of the…

• less than a min read
Whiteboard Wednesdays , ccix

Breakfast Bytes

Growth Comes from Solving New Problems—ESD Alliance CEO Panel

First, some sad news. Bob Gardner, for many years the executive director of the ESD…

• 12 min read
cadence , EDAC , arm holdings , ARM , synopsys , Breakfast Bytes , esd alliance , Mentor

Breakfast Bytes

Microsoft CDNLive Keynote: Cloudy with a Chance of Chips

Traditionally at CDNLive Silicon Valley, the first keynote is given by Lip-Bu Tan…

• 7 min read
microsoft , deep learning , cloud , azure , CDNLive Silicon Valley , Breakfast Bytes

Breakfast Bytes

The IRDS Panel at IRPS

Confused by those names? The conference is the International Reliability and Physics…

• 4 min read
irds , ITRS , international roadmap for devices and systems , irps , IEEE , Breakfast Bytes , rebooting computing

Whiteboard Wednesdays

Whiteboard Wednesdays - Convolutional Neural Network Challenges

In this week's Whiteboard Wednesdays video, Megha Daga takes a closer look at the…

• less than a min read
Whiteboard Wednesdays , convolutional neural networks

Breakfast Bytes

"The Safest Train Is One that Never Leaves the Station"

The Sunday and Monday at IRPS are tutorial days, with multiple tracks. On Monday…

• 7 min read
Automotive , functional safety , volkswagen , NVIDIA , sotif , ISO 26262 , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview May 1st to 5th 2017

https://youtu.be/n1uLybW0__s Coming from Millennium Park, Chicago (camera Jessamine…

• less than a min read
Physical verification , ieee 1800.2 , uvm , Genus , Embedded Vision Summit , pegasus , DRC , CDNLive EMEA , TSMC , via pillar , CDNLive Munich , Tensilica , design rule check , n7 , Innovus , cdnlive München , 7nm , vision processor

Breakfast Bytes

The $10 Raspberry Pi Zero W

Roger Thornton of the Raspberry Pi foundation talked about designing their latest…

• 6 min read
Raspberry Pi , raspberry pi zero w , bluetooth , PCB design , WiFi , Breakfast Bytes , Allegro

Verification

SoC Verification with Portable Stimulus Using Perspec System Verifier

This year’s CDNLive San Jose was another gem. Many great keynotes, customer presentations…

• 2 min read
SoC verification , Perspec , perspec system verifier , Qualcomm , portable stimulus

Breakfast Bytes

Software Isn't the S in SDE

System Design Enablement (SDE) is about designing optimal systems, focusing effort…

• 8 min read
SDE , open source , software , gcc , system design enablement , linux , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: Run Point Selection -WYSIWYG

With Virtuoso ADE Explorer and Virtuoso ADE Assembler , it is easy to create setups…

• 4 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , Mixed-Signal , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design

Breakfast Bytes

CCIX Is Pronounced C6

Cache coherency has become a big issue as the architecture inside devices such as…

• 4 min read
GPU , ccix , cache coherency , offload processors , Breakfast Bytes , FPGA
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