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Latest blogs

What's For Breakfast? Video Preview February 20th to 24th 2017

https://youtu.be/EVZ4T8TPim8 Coming from inside a Microsoft Hololens Monday…

Paul McLellan 13 Feb 2017 • less than a min read

holoens , DesignCon , spie advanced lithography , Mobile World Congress , MWC , rocketsim , target impedance , parallel simulation

Analog/Custom Design

Virtuoso Video Diary: Eye Masks

Have you ever plotted an eye diagram in Virtuoso Visualization and Analysis XL and…

TeamADE 13 Feb 2017 • 4 min read

Eye Mask , Analog Design Environment , Eye , ADE GXL , ViVa-XL , ADE Explorer , Analog Simulation , ADE XL , ADE , Virtuoso Analog Design Environment , ADE-GXL , Analog Design Environment , ViVA , ADE-XL , Virtuoso Video Diary

Breakfast Bytes

The Second Embedded Neural Network Symposium

A couple of weeks ago, Cadence held the second embedded neural network symposium…

Paul McLellan 13 Feb 2017 • 8 min read

deep neural networks , enns , dnn , embedded neural networks , neural networks

Breakfast Bytes

Integrated Bus Routing Solution

For most chips, the automatic routing in Innovus—NanoRoute—works well. But there…

Paul McLellan 10 Feb 2017 • 3 min read

integrated bus routing solution , grid-based routing , analog , Innovus , high frequency router

Breakfast Bytes

Circuits and Systems for Security and Privacy

One of the perks of writing this blog is that I get offered review copies of interesting…

Paul McLellan 9 Feb 2017 • 6 min read

security , side channel attacks , encryption , puf , crc press , random number , physically unclonable functions

Breakfast Bytes

Tom Quan on TSMC's Automotive Strategy

Tom Quan recently came to Cadence to talk about TSMC's automotive strategy. Tom and…

Paul McLellan 8 Feb 2017 • 4 min read

Automotive , tom quan , TSMC , 7ff , 16FFC , ISO 26262 , ADAS , 7nm , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview February 13th to 17th 2017

https://youtu.be/HL0GFG9tNP4 Coming from Cadence security camera Monday…

Paul McLellan 7 Feb 2017 • less than a min read

deep learning , machine learning , convolutional neural networks , moore's law , embedded neural networks , neural networks , machine vision

Whiteboard Wednesdays

Whiteboard Wednesdays - Simplify UVM Scoreboarding with Cadence VIP

In this week's Whiteboard Wednesdays video, principal AE Matt Diehl explains how…

References4U 7 Feb 2017 • less than a min read

Verification IP , Whiteboard Wednesdays , VIP , DisplayPort , Matt Diehl

Breakfast Bytes

He Who Goes First Loses, EDA Edition

Yesterday I wrote a post He Who Goes First...Loses about how being first isn't always…

Paul McLellan 7 Feb 2017 • 4 min read

point tools , hunters , EDA , ambit , farmers

Breakfast Bytes

He Who Goes First...Loses

There is a saying, of course, that he who goes first wins. And sometimes, and in…

Paul McLellan 6 Feb 2017 • 5 min read

apple pay , credit cards , m-pesa , tube , london tube

Breakfast Bytes

Handling Variability in the Modern Design Cycle

Igor Keller gave an internal presentation on Handling Variability in the Modern Design…

Paul McLellan 3 Feb 2017 • 6 min read

on chip variation , AOCV , STA , OCV , variability , voltage droop , static timing , layout dependent effects , miller capacitance , SOCV , crosstalk , slew , SSTA

Verification

Preview of an Exciting DVCon

In the overall world of EDA, the Design Automation Conference ( DAC ) is the biggest…

tomacadence 2 Feb 2017 • 3 min read

uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification