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DAC 2026 Wrap-Up: AI-Powered Engineering Moves from Vision to Workflow Reality

Every year, Design Automation Conference (DAC) brings big announcements, packed demos…

Veena Parthan
• 5 min read
Jasper Formal Verification Platform , featured , agentic ai , DAC 2026 , AI for design

Corporate News

Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution

Today, AI infrastructure is driving a fundamental shift in semiconductor design.…

Corporate
• 7 min read
featured , chiplets , infrastructure ai , SF2P , physical ai

Corporate News

Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

Breakfast Bytes

SEMICON Best of the West: Coventor

SEMICON West runs a sort of award program called Best of the West. Companies submit…

• 3 min read
semicon west , semi , Coventor , semulator3d , best of the west

Breakfast Bytes

Perspec Modeling

The post A Perspective on Perspec earlier this week introduced the idea of Perspec…

• 3 min read
Perspec , perspec system verifier , UML , system verilog

Analog/Custom Design

High-Sigma Showdown: Which Method is Better?

The adoption and usage of advanced node technology (16nm and below) has been extraordinary…

• 3 min read
variation tsmc hsmc sss sampling high sigma

Breakfast Bytes

What's for Breakfast? August 22nd

http://youtu.be/ZkZQAW6Gl7M Monday: At SEMICON West the winner of the "Best of…

• less than a min read
provisioning , security , Intel , CDNLive India , linley group , shockley , wearables , Qualcomm , Fairchild , a16z , cdnlive bengaluru , Coventor , mobile , Silicon Valley

Breakfast Bytes

Palladium and Protium Platforms, the Hardware Twins

The Palladium Z1 is an enterprise-level emulation system. If you don't already know…

• 4 min read
palladium z1 , Protium , Palladium , Emulation , FPGA prototyping

Breakfast Bytes

Omnia Simulation in Tres Partes Divisa Est

"Omnia Gallia in tres partes divisa est" were the opening words to Julius Caesar…

• 3 min read
verilog-xl , Verilog , rocketick , rocketsim , simulation

Whiteboard Wednesdays

Whiteboard Wednesdays - Tensilica Fusion G3 DSP Features and Benefits

In this week's Whiteboard Wednesdays video, Paul Garden provides more details on…

• less than a min read
Whiteboard Wednesdays , IP , Tensilica , Tensilica Fusion G3

Verification

10 New Protocols to Design and Integrate Your SoC in Record Time

This month we released 10 new Verification IP for leading-edge protocols! Did I say…

• 1 min read
SPI NAND , Verification IP , VIP , MIPI , DisplayPort , USB , DSI , octal spi , Ethernet , Tensilica , design , Type-C , and Verification IP , USB UFS

Breakfast Bytes

A Perspective on Perspec System Verifier

Today we have UVM, the universal verification methodology. This is great for verifying…

• 4 min read
Perspec , perspec system verifier , cache coherency , ARM , power

SoC and IP

Building the Cars of the Future

The big buzz in the automotive industry lately is autonomous driving vehicles. Companies…

• 3 min read
Verification IP , VIP , Automotive Ethernet , CAN , automotive electronics , Ethernet , Design IP and Verification IP , Lin

Breakfast Bytes

What's for Breakfast? August 15th

It's verification week this week, with 5 posts about various aspects of Cadence's…

• 1 min read
Breakfast Bytes

Breakfast Bytes

Verification Technology Update

At CDNLive in Bengaluru last week, Michal Siwiński gave a technology update on verification…

• 4 min read
Perspec , Protium , VIP , Palladium , Incisive , Indago , JasperGold , Breakfast Bytes , vManager , verification

Breakfast Bytes

5G, Coming Soon to a Phone Near You

At the Linley Mobile Conference recently, the morning after Linley's keynote was…

• 3 min read
5G , Linley , simultaneous connectivity , mobile , Breakfast Bytes

Verification

The Evolution of MIPI DSI

The MIPI DSI specification has come a long way from the days of its early introduction…

• 2 min read
Verification IP , MIPI Alliance , IoT , VIP , MIPI , DSI , Tensilica , design , Internet of Things , and Verification IP

Breakfast Bytes

CDNLive Bengaluru: Day 2

CDNLive Bengaluru takes place over two days. But it is organized very differently…

• 7 min read
NXP , CDNLive India , CDNLive , whats for breakfast , cdnlive bengaluru , implementation , tapeout

Breakfast Bytes

CDNLive Bengaluru: Day 1

As I did at the Design Automation Conference in Austin earlier this year, I will…

• 7 min read
CDNLive , bengaluru , bangalore , Breakfast Bytes , analog devices

Whiteboard Wednesdays

Whiteboard Wednesdays—Radar Signal Processing for Automotive Applications

In this week's Whiteboard Wednesdays video, the first of a two-part series, Pushkar…

• less than a min read
Automotive , DSP , Whiteboard Wednesdays , IP , radar , Tensilica

Breakfast Bytes

CDNLive Bengaluru, a Long Journey

I've not been to Bengaluru for about 20 years, when I ran engineering at Compass…

• 3 min read
CDNLive India , bengaluru , Cadence India , Breakfast Bytes

System, PCB, & Package Design 

Five Industry Experts Coming to CDNLive Boston to Discuss Signal and Power Integrity…

Who Are They? Istvan Novak – Senior Principal Engineer at Oracle Kevin Roselle…

• less than a min read
CDNLive , Signal Intregrity , Power Integrity , Boston , PCB design
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