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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Breakfast Bytes

ITF Keynote: IC Innovation—the Heartbeat of Yesterday, Today, Tomorrow

Luc van den Hove, the CEO of imec, gave the opening keynote at the imec Technology…

• 4 min read
Gordon Moore , neuromorphic computing , smart cities , IoT , system technology co-innovation , imec , itf brussels , Internet of Things , luc van den hove , moore's law , itf

Breakfast Bytes

Inside Secure Writes the Book on IoT Security for Dummies

At the Linley IoT conference recently, one of the presentations was by Steve Singer…

• 4 min read
security , data in use , data at rest , security for dummies , IoT , inside secure , Linley , iot security for dummies , data in motion , Breakfast Bytes , linley iot conference

Whiteboard Wednesdays

Whiteboard Wednesdays—Advantages of the MIPI I3C Interface

In this week's Whiteboard Wednesdays video, Alex Passi explains the advantages provided…

• less than a min read
mobile devices , Whiteboard Wednesdays , IP , MIPI , I3C

SoC and IP

16Gbps Multi-link, Multi-protocol SerDes at the 21st IEEE European Test Symposiu…

The 21 st European Test Symposium (IEEE EST) took place in Amsterdam (Netherlands…

• 1 min read
16gbps , PCIe Gen4 , SerDes , Multi-link , multi-protocol

Academic Network

DAC 2016—Student Activities and Scholarships

The Cadence Academic Network is the proud sponsor of all student activities and scholarships…

• 2 min read
DAC , Cadence Academic Network , dac53 , Design Automation Conference , 53dac

Analog/Custom Design

Virtuoso Video Diary: Tips and Tricks on Virtuoso Visualization and Analysis XL …

Virtuoso Video Diary is envisaged to be an online journal that will relay information…

• 6 min read
custom/analog , Analog Simulation , analog , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Breakfast Bytes

DAC: the Curtain Rises on the Cadence Theater

As in previous years, a highlight of the Cadence booth at DAC is the theater, where…

• 4 min read
DAC , Cadence Academic Network , Cadence Theater , dac53 , Design Automation Conference , 53dac

SoC and IP

What Memory Best Fits Your Application?

With highly effective DDR4 and LPDDR4 class memories, it’s not always easy to know…

• 1 min read
DDR4 , LPDDR4 , 4266 , 3200

Breakfast Bytes

Breakfast Bytes: Post #150

This is the 150th blog post here at Breakfast Bytes since I arrived at Cadence in…

• 3 min read
IP , EDA , Semiconductor , Breakfast Bytes

Breakfast Bytes

3D Xpoint: Is It a Game-Changer?

You have probably at least heard of 3D Xpoint. This is a memory technology jointly…

• 4 min read
Intel , Memory , Micron , flash , memory hierarchy , 3dx , DRAM , Breakfast Bytes , 3d xpoint

System, PCB, & Package Design 

What's Good About the Latest in ADW? The 16.6-2015 Release Has Several New Enhancements…

With the Allegro Design Workbench (ADW) 16.6-2015 release, you’ll have several new…

• 2 min read
PCB , Cadence Design Systems , Allegro Design Workbench , Library and design data management , Grzenia , Librarians , library , ADW

Breakfast Bytes

Andrew Kahng on Industry-Academia Cooperation

At CDNLive Silicon Valley, Professor Andrew Kahng of UCSD gave a presentation titled…

• 4 min read
ucsd , Cadence Academic Network , CDNLive , academia , kahng , CDNLive Silicon Valley

SoC and IP

Continued Strength of the Design&Reuse IP-SoC India

Design&Reuse events are always exciting for their draw of an IP-centric audience…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes

Verification

Simulation Acceleration—Maximizing Simulator Performance

"Simulation Acceleration” or “Accelerated Verification” are terms commonly used to…

• 4 min read
Specman , Functional Verification , e , specman elite , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Creating an Acceleration-Ready Simulation Environment with…

In this week's Whiteboard Wednesdays video, Ofer Steinberg explains how accelerated…

• less than a min read
accelerated VIP , Verification IP , Whiteboard Wednesdays , IP , VIP , Palladium XP , simulation , SystemVerilog UVM , verification

Breakfast Bytes

CDNLive: Routing at 10nm

At CDNLive Silicon Valley, Geeta Garg and Chad Hale of ARM, and Ming Yue of Cadence…

• 3 min read
CDNLive , Routing , implementation , 10nm

Breakfast Bytes

What Is RocketSim? Why Did Cadence Acquire Rocketick?

I talked to Uri Tal last week, who has just joined Cadence as a result of the Rocketick…

• 3 min read
dac2016 , gate-level simulation , DAC , Functional Verification , NVIDIA , RTL simulation , Incisive , dft simulation , rocketick , rocketsim , intel capital , Breakfast Bytes

Breakfast Bytes

Linley IoT Conference: Security and...Well, Just Security

Mike Demler gave the keynote at the Linley IoT conference a couple of weeks ago.…

• 5 min read
security , IoT , industrial , Linley , wearables , Internet of Things , power , consumer , Breakfast Bytes

Breakfast Bytes

It's HOT in Austin in June

Every DAC, Heart of Technology (HOT) organizes an event. This year it will be held…

• 2 min read
dac2016 , DAC , CASEA , HOT , Heart of Technology , Jim Hogan , Breakfast Bytes
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