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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Academic Network

Cadence Technology Days at MIET

On 21 April, Cadence and the Moscow Institute for Electronics Technologies (MIET…

• 1 min read
MIET , Cadence Academic Network , academic workshop , academia , Russia

Academic Network

Visiting KAUST

Cadence Academic Network is a worldwide activity; therefore, the team members are…

• 2 min read
university , Cadence Academic Network , academic workshop , KAUST

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Fiber Weave Effect—Zig-Zag Routing? New Capabilities…

The 16.6-2015 Allegro PCB Editor release introduces the interactive conversion of…

• 3 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , Routing , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Academic Network

Academic Track at CDNLive EMEA

From May 2 to May 4, Cadence once again hosted their hugely popular user conference…

• 2 min read
Cadence Academic Network , CDNLive , MEMS Design Contest , CDNLive EMEA

SoC and IP

Compatibility Is Good, But Compliance Is Better—Certifying for VESA DisplayPort

For all IP providers, the ultimate proof of quality of their product is certification…

• 1 min read
IP , Jacek Duda , DisplayPort , MHL , USB , compliance , VESA , HDMI , Alternate Mode , certification

Whiteboard Wednesdays

Whiteboard Wednesdays—Vision Systems and Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen discusses using neural networks…

• less than a min read
Whiteboard Wednesdays , vision systems , IP , Chris Rowen , Tensilica , neural networks

Breakfast Bytes

An Steegen: Controlling the Semiconductor Funnel

Last week I was in Belgium for imec's international technology forum (ITF). For me…

• 4 min read
itf2016 , IBM , an steegen , imec , 5nm , 7nm , 10nm

Analog/Custom Design

Virtuoso Video Diary: Redesigned Virtuoso Forms

Enhanced User Experience with Redesigned Virtuoso Forms Research and customer…

• 3 min read
gui , Redesigned Forms , Virtuoso Space-based Router , User Experience , Virtuoso Layout Suite L , Layout , Virtuoso , Schematic Editor , VLS L , user interface , Schematic

Breakfast Bytes

Securing the IoT for Billions of Possible Intrusion Points

At the Linley IoT conference a few weeks ago, one of the presentations was by NXP…

• 3 min read
security , NXP , linley group , encryption , Linley , Breakfast Bytes , linley iot conference

Breakfast Bytes

Lip-Bu's Fireside Chat with Ed Sperling—With Real Fire

Usually the phrase "fireside chat" is just a figure of speech, but Wednesday's came…

• 7 min read
Ed Sperling , DAC 2016 , DAC , EDA , Lip-Bu Tan , semiconductor IP , Design Automation Conference , Breakfast Bytes , 53dac

Breakfast Bytes

DAC News, Wednesday

The last day of the DAC tradeshow is the best...said nobody ever. After two days…

• 9 min read
DAC 2016 , DAC , Apple , AMD , Denali Party , dac53 , Lip-Bu Tan , netflix , Breakfast Bytes , 53dac

Breakfast Bytes

DAC News, Tuesday

Tuesday, the second day of DAC. Last night I learned that in Texas there is a third…

• 8 min read
DAC 2016 , DAC , risc-v , GPU , NVIDIA , dac53 , barbecue

Analog/Custom Design

Analog Design Resonance: When a Plan Comes Together

Yes, indeed, we all love it when a plan comes together. A plan for running all the…

• 3 min read
Run Plans , maestro , ADE , Virtuoso Analog Design Environment , Custom IC Design , ADE Assembler

Breakfast Bytes

DAC News, Monday

Monday is always a hectic start to DAC. If you have been in the industry for decades…

• 7 min read
dac2016 , DAC , NXP , Heart of Technology , lars reger , Lucio Lanza , cadence verification lunch , 53dac

Breakfast Bytes

DAC News, Sunday

Gary Smith EDA Traditionally the start of DAC is a short presentation by Gary…

• 5 min read
DAC 2016 , DAC , Gary Smith EDA

Verification

How to Find Where Declared e Entities Are Used

The e Reflection API allows you to perform various queries on entities in your own…

• 4 min read
IEEE 1647 , funtional verification , Specman , Functional Verification , e , e language , Funcional Verification , specman elite , IES

Breakfast Bytes

DAC: My Guide

DAC starts this weekend. So what should you go to? I'll tell you what my plans are…

• 3 min read
dac2016 , DAC , NVIDIA , Gary Smith EDA , Heart of Technology , Denali Party , dac53 , Cooley , 53dac

SoC and IP

DAC 2016—Drink from the Expert Bar and Then at the Denali Party

Black-belt interface and memory protocol technologists will be at your disposal at…

• 2 min read
DAC , IP , Denali Party , Denali

Verification

How to Maximize Your Verification Experience at DAC 2016

Next week will mark the annual EDA gathering in Austin. For me it is my 20th DAC…

• 13 min read
dac2016 , DAC , Verification Computing Platform , Protium , Palladium , Prtable Stimulus
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