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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Embedded Cavity DRCs? It's NEW in the 16.6 Release…

Max cavity size and max cavity component count were offered as reports in the 16…

• 1 min read
PCB , Routing , 16.6 , High Speed , SPB , PCB Editor , Layout , Grzenia , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—Specialty Memories

In this week's Whiteboard Wednesdays video, Lou Ternullo takes a closer look at what…

• less than a min read
Whiteboard Wednesdays , Memory , wide i/o , HMC , HBM

SoC and IP

Call for Papers for MemCon Closes This Friday

You still have a chance to get a paper accepted at the premier conference for memory…

• less than a min read
MemCon , memory technology , ip cores , memories

System, PCB, & Package Design 

BGA Ball Map Creation

Are you responsible for the creation and management of a BGA ball map or a die bump…

• 1 min read
Co-Design , IC package design , I/O planning , BGA ball map

Verification

Performance and the Use of Port mvl Lists (or, Nothing in Life is Free…)

When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But…

• 4 min read
performance , Specman , Functional Verification , Incisive , e , e language

System, PCB, & Package Design 

Designing a Complex Leadframe Package? See How SiP Layout Tool Can Cover All the…

Leadframe package designs are here to stay, and they are getting more complex with…

• 7 min read
IC Packaging and SiP Design , Cadence Design Systems , leadframe , SiP , Digital SiP design , design variants , IC package design , package design , SiP Layout , wirebonding

Verification

The Dark Side of Constraints on 'do-not-generate' Fields

The art of expressing hardware functionality through constraint language is often…

• 7 min read
IntelliGen , Specman , Functional Verification , e language , constraint coding

Verification

Debugging Multi-Language Verification Environments

As shown in previous blog posts in the Multi-Language Verification Environment series…

• 4 min read
uvm , UVM-ML , multi-language verification , debugging

Digital Design

Five-Minute Tutorial: Innovus Placement Optimization

Hi Everyone, Last time we got a quick look at The Innovus Standard Flow . Now…

• less than a min read
GigaPlace , Timing Optimization , Innovus , Placement

Whiteboard Wednesdays

Whiteboard Wednesdays—What Is PCI Express Address Translation Services?

In this week's Whiteboard Wednesdays video, Gopi Krishna defines and describes how…

• less than a min read
Whiteboard Wednesdays , address translation services , PCIe , PCI Express

SoC and IP

Find Everything You Need to Build an Advanced PCI Express 4.0 Solution in One Booth…

The PCI-SIG Developers Conference happening today and tomorrow will be yet another…

• 2 min read
PCIe Gen4 , pcie gen2 , 16nm , PCIe Gen3 , PCI-SIG

Analog/Custom Design

Things You Didn't Know About Virtuoso: Help Us to Help You

There is a team at Cadence working on developing the next generation of Cadence documentation…

• less than a min read
Virtuoso , Cadence Help , online documentation , Cadence support

System, PCB, & Package Design 

Manage All Design Variant Options for Your Package Substrate Seamlessly Using 16…

Stacked memory is becoming increasingly common in IC package substrates; with that…

• 2 min read
IC Packaging and SiP Design , stacked dies , SiP , IC Package , IC Packaging , SiP Design , design variants , package design , SiP Layout

SoC and IP

Sensor Processing, How Hard Can It Be?

When I think back back just a few years ago, there were only a handful of devices…

• 2 min read
DSP , IP , IP blocks , controller , IoT , SoC , Fusion , ip cores , Processor IP , Tensilica , semiconductor IP , Internet of Things , Design IP and Verification IP , always-on

Whiteboard Wednesdays

Benefits of Designing Your SoC with a Multi-Protocol PHY

In this week's Whiteboard Wednesday video, William Chen explains the many benefits…

• less than a min read
Whiteboard Wednesdays , IP , PHY , SoC , multi-protocol

SoC and IP

Tensilica Team Wins DAC 2015 Best Paper Award

Cadence’s Tensilica team was honored with the Best Paper Award at the IP track at…

• 1 min read
IP , Chris Rowen , ip cores , vision , imaging , image processing

Analog/Custom Design

Virtuosity: 14 Things I Learned in May 2015 by Browsing Cadence Online Support

Cadence Documentation 1. Cadence Documentation Survey Cadence is committed…

• 4 min read
ADE XL , Virtuoso , Spectre

Verification

Designing a Google Ara Module and Worrying About MIPI UniPro?

So you've looked at Google project ARA and you have the most brilliant idea for a…

• 1 min read
Verification IP , UniPro , Ara , VIP , MIPI , google , TripleCheck

Verification

Aargh!!! How Can I Read Arguments from the Command Line Without argv?

Many times a user would like to be able to modify the behavior of a program based…

• 3 min read
Specman , Functional Verification , e language , simulation
CDNS - Fix Layout Hompage