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Academic Network

Cadence Academic Network - The Next Generation

“University students around the world are using Cadence technology to learn and develop…

Anton Klotz 3 Dec 2015 • 2 min read

Cadence interns , Cadence Academic Network , EDA , engineering

System, PCB, & Package Design

What's Good About PCB Allegro Rules Developer and Checker? 16.6 Has It!

You can now leverage the 16.6-2015 release Allegro Rules Developer and Checker .…

Jerry GenPart 2 Dec 2015 • less than a min read

Constraint-driven PCB Design flow , Allegro GUI , Allegro 16.6 , Routing , electrical constraints , High Speed , PCB Editor , High-Density Interconnect , Layout , PCB design , Allegro PCB Editor , differential pairs

Breakfast Bytes

Why Do Layout Designers Say "Stream Out"?

For the same reason we "hang up" our phones. When a layout designer saves a design…

Paul McLellan 2 Dec 2015 • 6 min read

GDSII , Stream Out , Layout , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—DUT Verification with Cadence VIP

In this week's Whiteboard Wednesday's video, Arindam Guha explains how to quickly…

References4U 1 Dec 2015 • less than a min read

DUT verification , Verification IP , Whiteboard Wednesdays , VIP

SoC and IP

Will USB Type-C Connector Replace the 3.5mm Audio Jack?

In the past few days, there have been many posts on the Internet around Apple planning…

Jacek Duda 1 Dec 2015 • 1 min read

USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , Design IP and Verification IP , USB connector , USB 3.1

Breakfast Bytes

Virtuoso: Advance to 10nm, If You Pass Go Collect $200

There are two major discontinuities in the last couple of process nodes—FinFETs and…

Paul McLellan 1 Dec 2015 • 5 min read

EAD , FinFets , iPVS , Custom Routing , multi-patterning , Virtuoso , 10nm , modgens , color-aware layout , Breakfast Bytes

System, PCB, & Package Design

Take Tighter Control Over Your Shape Degassing Patterns with Cadence 16.6 Allegro…

With metal density and balancing requirements getting stricter with every year that…

ICPackagingPro 30 Nov 2015 • 6 min read

Cadence Design Systems , SiP Design , 16.6 , IC package design , APD , Allegro Package Designer , manufacturing , SiP Layout , shapes

Breakfast Bytes

TSMC 3D. Red and Green Glasses Not Required

I have been taking a look at TSMC's 3D packaging technologies. From numerous presentations…

Paul McLellan 30 Nov 2015 • 4 min read

CoWoS , 3DIC , info-pop , TSMC , InFO , info_s , Breakfast Bytes

Breakfast Bytes

Can You Pass As a Brit? Just Answer 3 Simple Questions

It’s Thankgiving! Happy Thanksgiving if you are reading this on the day. Cadence…

Paul McLellan 26 Nov 2015 • 9 min read

thanksgiving , lbw , guy fawkes , gunpowder plot , glorious revolution , marmite

Breakfast Bytes

Voltus-Fi: Faithful Custom and Analog EMIR and Power Analysis

First things first. Voltus and Voltus-Fi are two separate products. They are both…

Paul McLellan 25 Nov 2015 • 3 min read

Voltus-Fi , AMS , electromigration , custom , analog , Voltus , Virtuoso , analog mixed signal , IR drop , power , Breakfast Bytes , EMIR

SoC and IP

50 Gbps Ethernet is on the Way

Here is my report from the most recent IEEE 802.3 standards meeting, which was held…

ArthurM 24 Nov 2015 • 2 min read

Ethernet standards , Automotive Ethernet , IEEE 802.3 , Ethernet , Marris , 50G Ethernet

Verification

Cheating Tetris

Remember Tetris? We’ve all played it at some point in our lives. You know, the game…

rmathur 24 Nov 2015 • 2 min read

Verification Computing Platform , Palladium , Tetris , Emulation

Breakfast Bytes

The Design that Made ARM

I sat down with Simon Segars, the CEO of ARM last Friday. As I said yesterday, it…

Paul McLellan 24 Nov 2015 • 4 min read

Simon Segars , ARM7TDMI , ARM , Breakfast Bytes

Breakfast Bytes

Happy 25th Birthday, ARM

This week is ARM's 25th anniversary. It is actually on Friday, the 27th, but since…

Paul McLellan 23 Nov 2015 • 7 min read

ARM processor , Simon Segars , VSLI , ARM

Verification

A Coverage Time-Saving Tip

How often has this happened to you? You are re-using a part of a previous design…

John Brennan 20 Nov 2015 • 2 min read

IMC , coverage , Incisive Enterprise Simulator , Incisive , metric-driven verification , MDV , Incisive Enterprise Simulator (IES)

Breakfast Bytes

Marie Pistilli Passed Away

Marie Pistilli, who was injured in a car-crash in October (as I included in my first…

Paul McLellan 20 Nov 2015 • less than a min read

Breakfast Bytes

The CDMA Story and Qualcomm

When second generation cell-phone technology, GSM, was developed the biggest issue…

Paul McLellan 20 Nov 2015 • 4 min read

wireless , GSM , cdma , Qualcomm

Breakfast Bytes

Technology Transfer: The Stanford/Berkeley Model

At SEMICON West this year, I attended an interesting presentation by Steven Forrest…

Paul McLellan 19 Nov 2015 • 4 min read

marc andreessen , two cultures , Stanford , technology transfer , Berkeley , steven forrest , a16z , mosaic , andreeson , a16z podcast , cp snow

System, PCB, & Package Design

What's Good About Allegro PCB Designer Manufacturing Option? It's NEW in the 16.6…

Wow! There is an extremely powerful option available for PCB designers in the 16…

Jerry GenPart 18 Nov 2015 • 2 min read

PCB Layout and routing , manufacturing option , Allegro 16.6 , 16.6 , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

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