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SoC and IP

Mobile World Congress: Enabling Systems with Sensor Fusion, DSPs

BARCELONA, Spain—We hear a lot about sensor fusion and the applications that it can…

Brian Fuller 30 Mar 2015 • 1 min read

DSP , sensor fusion , #MWC15 , cadence , Freespace , Mobile World Congress , Tensilica , Hillcrest Labs

Digital Design

High-Level Synthesis: Why Now?

March 27, 2015 – With a title like “Why Now?”, you might expect this to be a sales…

dpursley 27 Mar 2015 • 2 min read

High-Level Synthesis , EDA , Forte , Stratus , HLS

Whiteboard Wednesdays

Whiteboard Wednesdays—The Power of WiGig (802.11ad)

In this week's Whiteboard Wednesdays video, Bob Salem explains WiGig (IEEE 802.11ad…

References4U 24 Mar 2015 • less than a min read

wireless , Whiteboard Wednesdays , interfaces , 802.11ad , wiGig

System, PCB, & Package Design

What's Good About Allegro PCB Editor Highlight Nets Associated with Component? It…

With the 16.6 Allegro PCB Editor release, a simplified method to highlight or de…

Jerry GenPart 24 Mar 2015 • less than a min read

PCB Layout and routing , Allegro GUI , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor

SoC and IP

Link Training: Establishing Link Communication Between DisplayPort Source and Sink…

Link training is the first stepping stone to enabling the communication channel between…

Neelabh 23 Mar 2015 • 2 min read

Verification IP , VIP , DisplayPort , Link Training , Design IP and Verification IP

SoC and IP

ARM-Cadence IP Deal Propels Engineering Innovation Ahead: Martin Lund

On March 18, Cadence and ARM announced a groundbreaking deal that provides reciprocal…

Brian Fuller 18 Mar 2015 • 6 min read

IP , electronic system design , cadence , systems engineering , IP design , ip cores , interoperability , ARM

Whiteboard Wednesdays

Whiteboard Wednesdays—Cognitive Layering Technique for Low-Energy, Sensor-Rich D…

In this week's Whiteboard Wednesdays video, Chris Rowen talks about techniques for…

References4U 18 Mar 2015 • less than a min read

Whiteboard Wednesdays , IP , IoT , sensors , Tensilica , always-on , power

SoC and IP

Mobile World Congress: Two New Audio IP Announcements

BARCELONA, Spain—Mobile World Congress is not surprisingly focused on mobile devices…

Brian Fuller 16 Mar 2015 • less than a min read

DTS , #MWC15 , cadence , audio , audio subsystems , Mobile World Congress , IP design , Tensilica , HiFi Audio , MaxxVoice

Whiteboard Wednesdays

Whiteboard Wednesdays—Major Enhancements of the PCIe Gen 4 Specification

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan talks about the…

References4U 10 Mar 2015 • less than a min read

Whiteboard Wednesdays , IP , PCIe Gen4 , bandwidth , PCI Express , power

Life at Cadence

A Great Place to Do Great Work: Celebrating Our First Year on the FORTUNE List of…

Innovation starts with our people. For over 25 years, Cadence has been a leader…

Tina Jones 5 Mar 2015 • 4 min read

cadence , Fortune , GPTW , Lip-Bu Tan , Fortune 100 best companies to work for , great place to work

SoC and IP

IP Requirements for Verifying CHI-Based Designs

Just as IP components offload design effort, verification IP (VIP) components offload…

DimitryP 4 Mar 2015 • 2 min read

Verification IP , Interconnect Validator , IVD , CHI , VIP , Design IP and Verification IP , CHI VIP

SoC and IP

Mobile World Congress: A Decade of Change in IP Innovation

BARCELONA, Spain—In the past decade, immense change has come to mobile electronic…

Brian Fuller 4 Mar 2015 • 1 min read

electronic system design , #MWC15 , cadence , Steve Roddy , Mobile World Congress , Tensilica , mobile , IC design

Analog/Custom Design

Virtuosity: 12 Things I Learned In February by Browsing Cadence Online Support

Application Notes 1. Voltus-Fi Power Analysis Support and Power Grid View Generation…

stacyw 4 Mar 2015 • 3 min read

AMS Designer , PSPICE , Voltus , Layout , Constraints , FinFET , VLS XL

SoC and IP

WiGig Has Arrived to Enable IoT Designs--and Cut the HDMI Cord!

What is WiGig WiGig is the name given to a high-speed multi-gigabit wireless communications…

Steve Brown 4 Mar 2015 • 3 min read

wireless , cadence , IP blocks , IP design , WiGig IP , 802.11ad , wiGig , HDMI , WiFi

Whiteboard Wednesdays

Whiteboard Wednesdays - Optimizing Power Via a Configurable Processor

In this week’s Whiteboard Wednesdays, Chris Rowen takes a look at the basic energy…

References4U 3 Mar 2015 • less than a min read

Whiteboard Wednesdays , IP , Chris Rowen , optimize power , Tensilica , energy , configurable processor , power

Analog/Custom Design

Virtuosity: 13 Things I Learned in January 2015 by Browsing Cadence Online Suppo…

'Tis the end of an era, folks. It should not be a surprise, but IC 5.1.41 reached…

stacyw 2 Mar 2015 • 2 min read

EAD , ADC , PLL , ADE , Spectre , Parasitic analysis

System, PCB, & Package Design

What's Good About Allegro PCB Editor Find Filter Support of Hierarchical Constraint…

The 16.6 Allegro PCB Editor release ‘Find by Name’ list now supports hierarchical…

Jerry GenPart 25 Feb 2015 • less than a min read

Cadence Design Systems , Allegro 16.6 , PCB Editor , PCB design , Grzenia , Allegro PCB Editor , Allegro

Verification

Don’t Lose Extra Simulation Cycles

After reading the rest of this blog, you might guess the truth, which is that my…

teamspecman 25 Feb 2015 • 2 min read

Specman , e , e verification code , simulation , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Cadence VIP Ease of Use Project

In this week's Whiteboard Wednesdays video, Herbert Rivera-Sanchez discusses the…

References4U 25 Feb 2015 • less than a min read

Verification IP , Whiteboard Wednesdays , IP , VIP , Ease of Use

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