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RF Engineering

How to Specify Phase Noise as an Instance Parameter in Spectre Sources (e.g. vsource…

Last year, I wrote a blog post entitled Modeling Oscillators with Arbitrary Phase…

Tawna 20 May 2014 • 1 min read

Spectre RF , phase noise , spectreRF , analogLib , port , noise profiles

Whiteboard Wednesdays

Whiteboard Wednesdays - Taking Command of MIPI PHYs - M-PHY

In this week's Whiteboard Wednesdays, the second installment of a three-party series…

References4U 20 May 2014 • less than a min read

mobile devices , Whiteboard Wednesdays , MIPI PHYs , M-PHY

SoC and IP

400G Task Force, 100G Backplane Project and Other Highlights from IEEE 802.3 Ethernet…

Here is another report from an IEEE 802.3 Ethernet standards meeting, this time held…

ArthurM 19 May 2014 • 2 min read

25G Ethernet , Ethernet standards , Automotive Ethernet , IEEE 802.3 , 100G backplane , 400G

Computational Fluid Dynamics

NASA Glenn Research Center: Integrated Fluid Dynamics – Acoustics Simulation Approach…

An innovative computational approach, integrating mesh generation, CFD simultaneous…

AnneMarie CFD 15 May 2014 • less than a min read

System, PCB, & Package Design

What's Good About Allegro PCB Editor Show Measure for Dual Units? 16.6 Has It!

The Allegro PCB Editor 16.6 ‘Show Measure’ command now displays results in database…

Jerry GenPart 13 May 2014 • 1 min read

PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , Routing , electrical constraints , SPB , PCB Editor , Layout , design , PCB design , physical layout design , Allegro PCB Editor , PCB Capture , Allegro

Analog/Custom Design

High Yield Analysis and Optimization - How to Design the Circuit to Six Sigma

Why high yield analysis? One failed memory cell out of millions cells will cause…

Hongzhou Liu 12 May 2014 • 2 min read

Six Sigma , Virtuoso , Circuit Design , analog design , high yield analysis

Verification

sync and wait Actions vs. Temporal Struct and Unit Members

Using sync on a temporal expression (TE), does not guarantee that the execution will…

teamspecman 12 May 2014 • 2 min read

AF , events , IntelliGen , Specman , units , e code , temporal expressions , Funcional Verification

Whiteboard Wednesdays

Whiteboard Wednesdays - Promises and Challenges of DDR4 Memory Technology

In this week's Whiteboard Wednesdays, Kishore Kasamsetty provides a history on DDR4…

References4U 12 May 2014 • less than a min read

memory protocols , Whiteboard Wednesdays , DDR4 , DDR3

RF Engineering

See Cadence RF Technologies at IEEE International Microwave Symposium 2014

RF Enthusiasts, Come connect with Cadence RF experts and discover the latest advances…

Nebabie 8 May 2014 • less than a min read

RF Simulation , IMS , RFIC , Spectre RF , Virtuoso , International Microwave Symposium , IEEE

SoC and IP

Don’t Miss Embedded Vision Summit West on May 29

Embedded Vision Summit West 2014 on May 29 at the Santa Clara Convention Center provides…

PaulaJones 7 May 2014 • less than a min read

Embedded Vision Summit , video , google , Facebook , Tensilica , vision , embedded vision technology , imaging

Whiteboard Wednesdays

Whiteboard Wednesdays - Verifying Your Designs with Simulation VIP

In this week's Whiteboard Wednesdays, Tom Hackett takes a closer look at simulation…

References4U 6 May 2014 • less than a min read

Verification IP , VIP , design verification , simulation VIP , PCI Express , protocol checks

Verification

e and SystemVerilog: The Ultimate Race

For years we've watched the e and SystemVerilog race via countless presentations…

Adam Sherer 6 May 2014 • 1 min read

IEEE 1647 , SystemVerilog , IEEE 1800 , simulation performance , e , Adam Sherer , UVM ML , Funcional Verification , IES

System, PCB, & Package Design

Add a View of Your Package Substrate in Your IC Layout Tool for Maximum Design Context…

We have all heard about co-design, how it is going to get us to market on time, reduce…

Jeff Gallagher 1 May 2014 • 4 min read

SiP , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout

Analog/Custom Design

How Can You Learn About Mixed-Signal Verification and Implementation Flows at Your…

The vast majority of SoCs today are advanced mixed-signal designs. The old mixed…

SumeetAggarwal 30 Apr 2014 • 3 min read

real number modeling , AMS Designer , EDA training , SV-RNM , DMS , mixed signal , Schematic Model Generator , RAKs

Whiteboard Wednesdays

Whiteboard Wednesdays—Wireless Transceiver Implementations

In this week's Whiteboard Wednesdays installment, Priyank Shukla highlights wireless…

References4U 29 Apr 2014 • less than a min read

RF , wireless , Whiteboard Wednesdays , IP , 802.11x , digital , AFE , LTE

System, PCB, & Package Design

What's Good About Allegro AMS Simulator PSpice Model Encryption? It’s in the 16.6…

With the 16.6 Allegro AMS Simulator (PSpice) release, you now have a new AES 256…

Jerry GenPart 29 Apr 2014 • less than a min read

AMS , Allegro 16.6 , AMS simulator , Allegro AMS , PSPICE , AMS simulation , model editor

Analog/Custom Design

What’s New in Virtuoso ADE XL in IC616 ISR6?

In a previous post, I explained the release model used for Virtuoso ADE and ViVA…

Tom Volden 28 Apr 2014 • 1 min read

Analog Design Environment , custom IC simulation , ADE XL , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Circuit Design , Custom IC Design , IC 6.1.6

RF Engineering

Broadband SPICE -- New Tool for S-Parameter Simulation in Spectre RF

Hi All, Here's another great new feature that I've found very helpful... Broadband…

Tawna 24 Apr 2014 • less than a min read

nport , Spectre RF , Broadband SPICE , nport settings , Spectre , s parameter simulation

RF Engineering

New Memory Estimator Helps Determine Amount of Memory Required for Large Harmonic…

Hi Folks, A question that I've often received from designers, "Is there a method…

Tawna 24 Apr 2014 • 1 min read

HB , Spectre RF , MMSIM , spectreRF , harmonic balance , memory estimator

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