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Whiteboard Wednesdays

Whiteboard Wednesdays - Taking Command of MIPI PHYs

In this week's Whiteboard Wednesdays installment, Kevin Yee discusses what it means…

References4U 22 Apr 2014 • less than a min read

mobile devices , Whiteboard Wednesdays , D-PHY , MIPI protocols , MIPI PHYs

Analog/Custom Design

Keeping Your Circuit in Tune: Sensitivity Analysis and Circuit Optimization

Anyone who has ever played a musical instrument knows how hard it can be to keep…

stacyw 21 Apr 2014 • 4 min read

Variability Aware Design , ADE GXL , worst case corners , optimization , Virtuoso , statistical corners , Variation

Analog/Custom Design

Virtuosity: 15 Things I Learned in March 2014 by Browsing Cadence Online Support

Highlights for this month include lots of useful Physical Verification System (PVS…

stacyw 15 Apr 2014 • 2 min read

Variability Aware Design , ADE GXL , Virtuoso , Analog Design Environment , PVS

System, PCB, & Package Design

What's Good About Capture’s Auto Part Reference? 16.6 has a Few New Enhancements

The 16.6 release of OrCAD Capture has a couple new productivity enhancements centered…

Jerry GenPart 15 Apr 2014 • less than a min read

capture , Cadence Design Systems , Allegro Design Entry , Design Entry CIS , cadence , Allegro Design Entry CIS , AMS simulator , OrCAD Capture , 16.6 , Capture CIS , Capture-CIS , OrCAD , PCB design , Design Entry , Grzenia , PCB Capture , Schematic

Analog/Custom Design

What's New(-ish) in ADE XL in IC 616 ISR 3?

Development Model for ADE and ViVA Virtuoso Analog Design Environment (ADE) and…

Tom Volden 15 Apr 2014 • 1 min read

Analog Design Environment , ADE XL , Custom IC Design , IC 6.1.6

Whiteboard Wednesdays

Whiteboard Wednesdays - How IP Enhances Hosted Virtual Desktops

In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application…

References4U 15 Apr 2014 • less than a min read

server virtualization , virtualization , IP , hosted virtual desktop , mobile workforces , BYOD

Verification

Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing…

In my first blog of this quarterly series, I focused on how Rapid Adoption Kits …

SumeetAggarwal 15 Apr 2014 • 6 min read

IMC , low power simulation , uvm , Specman , LPS , x-propagation , RAK , incisive simulation , LSF , Glitches , state retention , drm , SystemC , vMananger , IES-XL

Digital Design

Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support

Friends, you would probably agree that sharing knowledge is a practical way to solve…

MJ Cad 14 Apr 2014 • 2 min read

EDI , Encounterer Digital Implementation System , Digital Implementation forums , Tempus , EDI system , Cadence Online Support , digital implementation , Digital Implementation , Encounter Digital Implementation , signoff , timing signoff

Verification

Applying Software-Driven Development Techniques to Testbench Development

Over the past couple of years there has been some interest in applying a software…

teamspecman 9 Apr 2014 • 1 min read

AF , Specman , debug , e code , Funcional Verification , unit testing , Incisive Enterprise Simulator (IES)

System, PCB, & Package Design

OrbitIO/SIP-XL Co-Design Flow Highlighted at CDNLive SV 2014

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of…

TeamAllegro 8 Apr 2014 • 1 min read

SiP , DDR interface , CDNLive , Co-Design , IC package design , OrbitIO

Whiteboard Wednesdays

Whiteboard Wednesdays - Comparing 3D Memory Solutions and Their Market Applicati…

In this week's Whiteboard Wednesdays, Scott Jacobson completes his three-part series…

References4U 8 Apr 2014 • less than a min read

Whiteboard Wednesdays , 2D Memory , 3D memory , memory wall , SoC design

Analog/Custom Design

Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic…

Lorenz 2 Apr 2014 • 2 min read

ADE GXL , ADE XL , mismatch variation , Virtuoso Analog Design Environment , Monte Carlo , mismatch contribution analysis

Whiteboard Wednesdays

Whiteboard Wednesdays - Understand USB Controllers and Their Performance Specs

In this week's Whiteboard Wednesdays, Jacek Duda provides an informative overview…

References4U 1 Apr 2014 • less than a min read

USB performance specs , Whiteboard Wednesdays , IP , USB 3.X , USB controllers , USB 2.0

System, PCB, & Package Design

Cadence Sigrity Full-Wave 3D Field Solver Technology Highlighted at CDNLive SV 2…

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of…

TeamAllegro 28 Mar 2014 • 2 min read

single and multi-fabric design , full wave 3D field solver , Power Integrity , IC package design , 3DEM , Signal Integrity

System, PCB, & Package Design

Balance Metal Coverage Across Different Layers with Ease Using Cadence 16.6 IC Packaging…

To maximize yield and achieve optimum quality of your final, manufactured IC package…

Jeff Gallagher 26 Mar 2014 • 4 min read

IC Packaging and SiP Design , SiP , IC Package , IC Packaging and SiP , IC package design , IC Packaging & SiP design , IC packaging documentation , substrate , SiP Layout

Whiteboard Wednesdays

Whiteboard Wednesdays—The Exploding Variety of New Interfaces for Mobile SoCs

In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of…

References4U 25 Mar 2014 • less than a min read

LPDDR4 , LPDDR , wide i/o , USB , UFS , eMMC , DRAM , AMBA 5 , OCP , Wide I/O2 , CSI-3 , DDR , Soundwire , PCIe and SSIC. , AMBA 4 , eMMC5 , LPDDR3

System, PCB, & Package Design

What's Good About DEHDL “How To” Videos? The Secret's in the 16.6 Release!

While there are several videos available for Allegro Design Entry HDL (DEHDL) in…

Jerry GenPart 24 Mar 2014 • 1 min read

PCB , Allegro Design Entry , Allegro 16.6 , PCB design videos , electrical constraints , flat schematics , hierarchical schematics , Allegro 16.5 , SPB , Design Entry HDL , Design Entry , ConceptHDL

Analog/Custom Design

Efficient Design Migration Using Virtuoso Analog Design Environment GXL

Requirements for decreased time to market, reduced silicon area, and minimized power…

Tom Volden 21 Mar 2014 • 2 min read

Analog Design Environment , ADE GXL , ADE XL , Virtuoso , Custom IC Design , Design Migration

System, PCB, & Package Design

What's Good About ADW’s Board File Management? 16.6 Has a Few New Enhancements!

There are two new use models for PCB designers using Allegro Design Workbench (ADW…

Jerry GenPart 18 Mar 2014 • 1 min read

PCB , PCB Layout and routing , Allegro 16.6 , Allegro Design Workbench , PCB Editor , design data management , design , PCB design , Allegro PCB Editor , ADW

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