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Configurable Specman Messaging Webinar Archive Available Now

Configurable Specman Messaging for Improved Productivity Webinar Archive Available…

teamspecman 27 Aug 2013 • 1 min read

IEEE 1647 , Specman/e , AVS , Functional Verification , Specman e , Testbench simulation , Incisive Enterprise Simulator , e-language , configurable messaging , EDA , e , webinar , e language , Specman messaging , Specman C

System, PCB, & Package Design

Create Optimum Pin Assignments for FPGAs on PCBs - Part 1 of 2

In most FPGA-based boards, the PCB designer is on his own -- with little help from…

briggins 27 Aug 2013 • 5 min read

FPGA: ASIC Prototype , FPGA-PCB Co-Design , FPGA System Planner , FPGAs , FSP , pinswap , "PCB design" , PCB design , pin planning , pin swap , FPGA , FPGA Pin Assignment , FPGA: PCB

System, PCB, & Package Design

What's Good About FSP’s Allegro PCB Editor Board Import? 16.6 Has It!

The Allegro FPGA System Planner (FSP) has the ability in the 16.6 release to import…

Jerry GenPart 19 Aug 2013 • 5 min read

PCB , PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , cadence , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , Taray , FPGAs , SPB , PCB Editor , Layout , design , FSP , "PCB design" , PCB design , Grzenia , Allegro PCB Editor , FPGA , Allegro , FPGA: PCB

System, PCB, & Package Design

Enhance Your Packaging Documentation Outputs with the New SKILL Spreadsheet API Tools…

Spreadsheets, we all use them, and many of us do so daily. They are an efficient…

Jeff Gallagher 16 Aug 2013 • 3 min read

IC Packaging and SiP Design , SiP , IC Package , IC Packaging , packaging , Digital SiP design , 16.6 , IC Packaging and SiP , IC package design , APD , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout , IC Package Physical layout and co-design , cavity

Verification

Getting Ready for ESL with Emulation!

Next week on Monday, August 19th, Gary Smith will run a webinar called " ESL - Are…

fschirrmeister 12 Aug 2013 • 2 min read

Low Power , FPGA Based Prototyping , Verification Computing Platform , Virtual System Platform , cadence , Acceleration , System to Silicon Verification , Dynamic Power Analysis , System Design and Verification , System Development Suite , embedded software , Gary Smith , GSEDA , Palladium XP , Emulation , Atrenta , Schirrmeister , ESL , low power optimization

Analog/Custom Design

Virtuosity: 16 Things I Learned in July by Browsing Cadence Online Support

Feeling a bit lazy this month, but even without digging too deeply, I could find…

stacyw 12 Aug 2013 • 2 min read

AMS , mixed-signal simulators , custom/analog , Virtuoso Space-based Router , Routing , Rapid Adoption Kit , MMSIM , Mixed-Signal , Virtuoso , Schematic Editor , Virtuosity , AMS simulation , mixed signal , Modeling , Custom IC Design , space based router

System, PCB, & Package Design

What's Good About Allegro PCB Enhanced Object Filtering? See for yourself in 16.6

The 16.6 Allegro PCB Editor release provides enhanced Object Filtering to control…

Jerry GenPart 12 Aug 2013 • 2 min read

PCB , PCB Layout and routing , Cadence Design Systems , diff pairs , constraint databases , Allegro GUI , Allegro 16.6 , cadence , DEHDL , electrical constraints , object visibility layers , 16.6 , property , diff pair , SPB , PCB Editor , Constraint Manager , Design Entry HDL , differential pair , Layout , Xnets , design , "PCB design" , PCB design , Design Entry , Constraints , Grzenia , Allegro PCB Editor , differential pairs , Differential Pair Support , ConceptHDL , PCB Capture , Allegro

System, PCB, & Package Design

What's Good About AMS Schematic Undo? It’s in the 16.6 Release!

Just a very brief post this week on a new AMS Simulator (PSpice) capability. The…

Jerry GenPart 12 Aug 2013 • less than a min read

capture , AMS , Allegro 16.6 , cadence , AMS simulator , OrCAD Capture , 16.6 , Capture CIS , PSPICE , OrCAD , AMS simulation , Grzenia

System, PCB, & Package Design

What's Good About RF PCB Libraries? 16.6 Has a Few New Enhancements!

There have been a few new library level enhancements made to 16.6 Allegro RF PCB…

Jerry GenPart 5 Aug 2013 • 1 min read

PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , RF PCB , cadence , Agilent , 16.6 , SPB , PCB Editor , Layout , design , PCB design , Grzenia , physical layout design , Allegro PCB Editor , Librarians , Agilent ADS , library

System, PCB, & Package Design

What's Good About PCB SI Channel Analysis? 16.6 Has Many New Enhancements!

There are several new enhancements associated with the 16.6 PCB SI Channel Analysis…

Jerry GenPart 30 Jul 2013 • 5 min read

PCB SI , SI , Cadence Design Systems , Allegro 16.6 , cadence , Signal Intregrity , SigXP UI , 16.6 , "PCB SI" , High Speed , SPB , signal integrity analysis , Signal Integrity , "channel analysis" , design , "PCB design" , Allegro PCB SI , Grzenia , SI analysis and modeling

Verification

New Specman Coverage Engine (Part III)—Use of Extension Under "when" vs. Using Instance…

In both previous coverage blog posts ( Part I and the Part II ), we showed two solutions…

teamspecman 25 Jul 2013 • 2 min read

AF , e language , Funcional Verification , coverage driven verification (CDV) , Aspect Oriented Programming

System, PCB, & Package Design

What's Good About Allegro PCB Editor Parameterized Cornering? Check Out 16.6!

The Shape - Add Rectangle command has been enhanced in the 16.6 Allegro PCB Editor…

Jerry GenPart 23 Jul 2013 • 1 min read

polygon , PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , 16.6 , SPB , PCB Editor , setup , parameterized cornering , Layout , design , PCB design , Grzenia , Allegro PCB Editor , Allegro , etch shapes

Verification

New Specman Coverage Engine (Part II) - Using Instance-based Coverage Options for…

In the last coverage blog , we showed how the extensions of covergroups under when…

teamspecman 23 Jul 2013 • 3 min read

AF , coverage parameterization , Specman , coverage , covergroups , instance-based coverage , subtypes , e language , extensions under subtypes , Funcional Verification , Incisive Enterprise Simulator (IES)

Verification

Fujitsu Gets 3x Faster Regression with Incisive Simulator and Enterprise Manager

Verification regression consumes expensive compute resources and precious project…

Adam Sherer 23 Jul 2013 • 2 min read

performance , IEM , Enterprise Manager , simulation , Regression Farm , IES-XL

System, PCB, & Package Design

What's Good About ADW’s Flow Manager? 16.6 Has Many New Enhancements!

The 16.6 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide…

Jerry GenPart 23 Jul 2013 • 2 min read

PCB , Allegro Design Entry , Allegro 16.6 , cadence , 16.6 , Directive Lockhing , Allegro Design Workbench , Library flow , color , Team design , Library and design data management , SPB , PCB Editor , Design Entry HDL , Layout , design , PCB design , Design Entry , Grzenia , ConceptHDL , library , Schematic , Allegro

Verification

Verification IP: Five More Things I Learned By Browsing Cadence Online Support

After talking about some tips for using trace files in debugging Verification IP…

SumeetAggarwal 16 Jul 2013 • 4 min read

Verification IP , NVMe , NVMe PureView VIP Usage , Instantiating VIP models with SystemVerilog , USB , Denali Migration Guide , Integrating USB 3.0 PHY DUT , PHY DUT , Verification Flow USB , PureView USB 3.0 VIP.

Analog/Custom Design

Coming Soon: Asia-Pacific Mixed Signal Summit and Tech-On-Tour Events

Cadence is bringing the Analog/Mixed-Signal Summit to Shenzhen, China, and the Mixed…

Sathish Bala 15 Jul 2013 • 1 min read

conformal , SystemVerilog , EAD , AMS , EDI , Low Power , IP , Penang , Technology on tour , mixed-signal ToT , Cadence events , tech on tour , AMS Designer , behavioral modeling , Encounter Digital Implemenation , Advanced Node , analog , Incisive , Shenzhen , LDE , analog/mixed-signal , Virtuoso , mixed-signal summit , RNM , mixed signal , SMG , Cadence Community , Singapore , verification

Analog/Custom Design

Virtuosity: 20(!) Things I Learned in June by Browsing Cadence Online Support

Wow! There was an amazing amount of new content added last month. A lot of new videos…

stacyw 15 Jul 2013 • 2 min read

AMS , Low Power , Virtuoso Space-based Router , VSR , MMSIM , SKILL for the Skilled , Virtuoso , Schematic Editor , Virtuosity , mixed signal , SKILL++ , Virtuoso Layout Suite , SKILL , Schematic

System, PCB, & Package Design

Customer Support Recommended - Working with NetGroups in Allegro Design Entry CI…

Allegro Design Entry CIS provides a new feature called NetGroup, which offers an…

Naveen 9 Jul 2013 • 4 min read

PCB , Allegro 16.6 , Allegro Design Entry CIS , NetGroups , PCB design , vectors , buses , Schematic , hierarchical block , scalars , Allegro

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