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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Verification

Planes, Trains and Automobiles: European Seminar Series

A couple of blog posts ago, I talked about the worldwide functional verification…

• 3 min read
Functional Verification , Europe , formal , Incisive , Mixed-Signal , EMEA , metric-driven verification , MDV , IEV , IFV

Verification

Video: Update on AMIQ’s DVT IDE at DAC 2011 – Specman Debugger Integration, Open…

Specmaniacs and IES-XL users around the world know that Integrated Development Environment…

• less than a min read
DAC , eclipse , uvm , Specman , Functional Verification , Amitroaie , OVM , e , DVT , e language , AMIQ , eRM , IDE , verification , IES-XL

Verification

Video: Formal Verification Service Provider Oski Technology at DAC 2011

At DAC 2011, both myself and fellow Team Verify member Tom Anderson felt a distinct…

• 1 min read
DAC , ABV , verification strategy , Verification methodology , Functional Verification , Formal Analysis , formal , Oski Technology , assertions , Formal verification , verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Associative Dimensioning? Check Out 16.5!

With the Allegro PCB Editor SPB16.5 release we've enhanced the existing Allegro drafting…

• 3 min read
PCB , PCB Layout and routing , Routing , Allegro 16.5 , PCB Editor , Layout , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Analog/Custom Design

How to Design Analog/Mixed Signal (AMS) at 28nm

Wireless, networking, storage, computing and FPGA applications have been moving…

• 3 min read
AMS , AMS v2.0 , APS , Virtuoso-AMS , IP , AMS-Designer , reference flow , 28nm , TSMC , analog , Mixed-Signal , LDE , Virtuoso , Spectre , mixed signal

Verification

Photo Essay and Comments on DAC 2011 in San Diego, CA

In addition to the annotated image gallery ( click here or on the image), below are…

• 2 min read
DAC , Joe Hupcey III , ABV , asssertion-based verification , Formal Analysis , formal , EDA360 , EDA , ADS , Oski Technology , Assertion-Driven Simulation , Formal verification , cloud computing

Digital Design

Five-Minute Tutorial: Find A Pin's Transition Time

How many times while working in Encounter Digital Implementation system have you…

• 1 min read
EDI , max_transition , report_constraint , encounter , Digital Implementation , five minute tutorial , pin transition time

Analog/Custom Design

Mixed-Signal Physical Design Implementation Made Easy

Getting a complex mixed-signal design assembled and completely analyzed for mask…

• 2 min read
Low Power , IC 6.1 , Floorplanning , Mixed-Signal , encounter , Virtuoso , mixed signal , OpenAccess , design implementation

Verification

Is e Old? Yes. Is it Outdated? Definitely Not!

I was at the Design Automation Conference (DAC) last week showcasing our latest,…

• 2 min read
IEEE 1647 , DAC , Object Oriented Programming , Corey Goss , EDA , e , team specman , Aspect Oriented Programming , eRM , AOP

Analog/Custom Design

Virtuoso Analog Design Environment XL – Make Friends with Variation

In my last blog, Virtuoso Analog Design Environment XL - Embrace the Productivity…

• 3 min read
PVT , Analog Design Environment , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Analog Simulation , Corners analysis , analog , IC 6.1.5 , ADE , worst case corners , Virtuoso Analog Design Environment , Monte Carlo , Virtuoso , ADE-GXL , ADE-XL , Custom IC Design

RF Engineering

Q&A: TI Wireless Team Describes Advanced Phase-Noise Characterization for RF Oscillators…

In this interview, members of the Texas Instrument wireless group talk about the…

• 8 min read
RF , analog/RF , APS , Circuit simulation , characterization , HB , MMSIM , pnoise , phase noise , analog , Nand Jha , spectreRF , Spectre , Ted Blank , harmonic balance , Texas Instruments , VCO , pss , TI , Oscillator

System, PCB, & Package Design 

What's Good About Allegro PCB Editor IDX Support? Look to SPB16.5 and See!

The Allegro 16.5 release was made available on May 17, 2011! This release adds additional…

• 6 min read
PCB , PCB Layout and routing , EDMD , Routing , MCAD , Allegro 16.5 , PCB Editor , Layout , IDX , IDF , "PCB design" , PCB design , SPB16.5 , Allegro

Verification

Looking Back at DAC

Last week was the 48 th Design Automation Conference (DAC), held in lovely San…

• 3 min read
DAC , uvm , Functional Verification , Formal Analysis , Denali Party , San Diego , Design Automation Conference

Verification

A SystemC Virtual Platform Overflowing the Stack -- Just Before DAC

Thanks to all who stopped by the Cadence booth to see and talk about the Cadence…

• 6 min read
DAC , Virtual System Platform , virtual platforms , virtual prototypes , Demo , stack overflow , SystemC , System Design and Verification

Verification

Using the ARM Profiler with the Cadence Virtual System Platform

I have posted a new article over at blogs.arm.com covering the current integration…

• less than a min read
Virtual System Platform , virtual platforms , ARM Profiler , virtual prototypes , proflling , software , System Design & Verification , ARM

Verification

Image Gallery: Cadence-Denali Party at DAC 2011 in San Diego

The 20nm roadmap . TSMC reference flow 12 . The UVM 1.1 release . Verification IP…

• 1 min read
gallery , DAC , uvm , ACE , Joe Hupcey III , ABV , images , Functional Verification , Cadence VIP portfolio , formal , VIP , 20nm , EDA360 , TSMC , Denali Party , EDA , ADS , Denali , party , assertions , ARM , Assertion-Driven Simulation , Formal verification , Assertion-based verification

System, PCB, & Package Design 

Robert Hanson and Cadence Co-Host Signal Integrity Event in Massachusetts

In response to the OrCAD and Allegro 16.5 product release, and the growing demand…

• 1 min read
Allegro 16.5 , OrCAD PCB SI , Allegro PCB SI

Verification

DAC Cheesy Must See List: Enterprise Manager

Understandably, EDA industry observer John Cooley had to edit down all the submissions…

• 1 min read
Functional Verification , Metric Driven Verification , Enterprise Manager , MDV

Verification

DAC Preview: The Complete Incisive Enterprise Verifier Submission to John Cooley…

Understandably, EDA industry observer John Cooley had to edit down all the submissions…

• 1 min read
DAC , Joe Hupcey III , ABV , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , EDA , Incisive , ADS , Tom Anderson , SVA , Chris Komar , PSL , assertions , gadfly , MDV , IEV , Assertion-Driven Simulation , Formal verification , IFV , Assertion-based verification
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