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Photo Essay, Video Playlist, and Comments on DVCon 2012

In addition to the annotated image gallery (click here or on the image), or the playlist…

jvh3 12 Mar 2012 • 3 min read

NextOp , uvm , Low Power , Joe Hupcey III , ABV , videos , Yunshan Zhu , Functional Verification , Formal Analysis , ABVIP , video , formal apps , Vigyan Singhal , Chris Komar , Oski Technology , UCIS , DVcon , assertion synthesis , robot , Assertion-Driven Simulation , Formal verification , Assertion-based verification

Digital Design

Five-Minute Tutorial: Selective Blockage In EDI 11

Today I'd like to highlight one of the new features in Encounter Digital Implementation…

Kari 12 Mar 2012 • 1 min read

selectiveBlockage , EDI , EDI 11.1 , Encounter Digital Implementation11 , encounter , setPlaceMode , selective blockage , five minute tutorial , EDI 11 , placement blockage

Verification

DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Ap…

In this interview Product Engineer Chris Komar recaps the tutorial on formal apps…

TeamVerify 8 Mar 2012 • less than a min read

Low Power , Joe Hupcey III , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , formal apps , Chris Komar , DVcon , apps , assertion synthesis , assertions , IEV , Assertion-Driven Simulation , Formal verification , IFV , verification , Assertion-based verification

Analog/Custom Design

Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley…

QiWang 7 Mar 2012 • 2 min read

real number modeling , APS , Low Power , mixed signal design , CDNLive SV 2012 , parasitic , IC 6.1 , AMS Designer , CPF , analog , Mixed-Signal , analog behavoral , Virtuoso , RNM , CDNLive! , mixed signal , simulation , verification

RF Engineering

Guidelines for Maximizing Speed vs. Accuracy in SpectreRF simulations - Part 3

Several months ago, I started a 3 part series on Guidelines for Maximizing Speed…

Tawna 7 Mar 2012 • 4 min read

RF , RF Simulation , analog/RF , Circuit simulation , RFIC , QPSS Analysis , shooting newton , HB , Spectre RF , spectre spectreRF , Analog Simulation , MMSIM , RF spectre spectreRF , harmonic trimming , spectreRF , RF design , harmonic balance , mixer

System, PCB, & Package Design

What's Good About Allegro PCB Router Staggered Via Rules? See for yourself in 16

Just a quick blog today on a new 16.5 Allegro PCB Router enhancement for Staggered…

Jerry GenPart 6 Mar 2012 • 1 min read

PCB , PCB Layout and routing , global route , Routing , staggered vias , Allegro 16.5 , via rules , PCB Editor , Layout , vias , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Verification

Differentiation Through Hardware is Not Going Away

Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design…

Jack Erickson 5 Mar 2012 • 5 min read

High-Level Synthesis , 4G , TLM , hardware , android , system realization , hardware-dependent software , SoC , sub-systems , Quad-HD , iOS , software , DVcon , SystemC , smartphones , tablets

Digital Design

Five-Minute Tutorial: Where To Find More Encounter Digital Implementation (EDI) System…

We've had some people joining the forum lately that are either brand-new to Encounter…

Kari 5 Mar 2012 • 1 min read

video , tutorial , beginner , training , EDI 10.1 , Digital Implementation , init_design , five minute tutorial , EDI 11 , mmmc

System, PCB, & Package Design

What's Good About Allegro DFM/DRC Updates? 16.5 Has a Few New Enhancements!

Allegro PCB Editor has been enhanced in the 16.5 release with three (3) additional…

Jerry GenPart 28 Feb 2012 • 3 min read

PCB , PCB Layout and routing , DFA , backdrill , DRC , ADRC , Allegro 16.5 , SPB , PCB Editor , Layout , assembly DRCs , backdriling , design , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Analog/Custom Design

Virtuoso AMS Designer Wins the China ACE Best EDA Product Award

The China Annual Creativity in Electronics (ACE) Awards was established to recognize…

QiWang 28 Feb 2012 • less than a min read

AMS , Virtuoso-AMS , China , mixed signal design , ACE award , AMS-Designer , AMS Designer , Mixed-Signal , wreal

Digital Design

Five-Minute Tutorial: Default Naming Conventions in Encounter Digital Implementation…

This is a topic that frequently comes up on both internal and external forums. And…

Kari 27 Feb 2012 • 2 min read

EDI , naming , timing debug , tutorial , encounter , Digital Implementation , Encounter Digital Implementation , default naming conventions , five-minute

System, PCB, & Package Design

Altera 28 Gbps Stratix V IBIS-AMI Models Now Blazing Channels with Allegro PCB S…

Altera and Cadence recently collaborated and completed correlation work with Allegro…

TeamAllegro 24 Feb 2012 • 2 min read

PCB SI , PCB , Stratix V , Multi-Gigabit , Altera , IBIS , model kit , PCB power integrity , FPGAs , IBIS-AMI , Signal Integrity , PCB design , channel analysis , SI analysis and modeling , FPGA , Allegro

Verification

Virtual Divide and Conquer Enables Fixed Sub-Systems

The 17th North American SystemC User Group meeting ( NASCUG ), will take place this…

fschirrmeister 23 Feb 2012 • 3 min read

IP , zynq , virtual platforms , TLM , platform , virtual prototypes , fixed sub-systems , sub-systems , Tensilica , subsystems , OMAP , DVcon , SystemC , xilinx , NASCUG , FPGA , System Design and Verification , verification

Verification

Gentlemen, Start Your Simulation Engines

As we outlined in our recent performance white paper , every verification team has…

Adam Sherer 22 Feb 2012 • less than a min read

performance , SystemVerilog , Multi-Core , Incisive , Funcional Verification , Incisive Enterprise Simulator (IES) , IES , IES-XL

System, PCB, & Package Design

What’s Good about OrCAD Apps? Symbol and Footprint Creation Just Got a Lot Easier…

Creating the symbols and footprints necessary to complete your designs can be a difficult…

Jerry GenPart 21 Feb 2012 • 2 min read

PCB , Marketplace , OrCAD Capture Marketplace , Footprint , OrCAD Capture , Capture CIS , Capture-CIS , OrCAD online store , Library flow , Allegro 16.5 , Library and design data management , SPB , webinar , symbol , OrCADapps , "PCB design" , OrCAD , PCB design , Design Entry , SPB16.5 , Librarians , library , PCB Capture , Schematic , Allegro

System, PCB, & Package Design

What's Good About Capture’s Placement Report? Look to SPB16.5 and See!

The 16.5 release of OrCAD Capture includes the ability to generate a report with…

Jerry GenPart 21 Feb 2012 • less than a min read

"capture CIS" , Allegro Design Entry , hierarchy , Design Entry CIS , flat schematics , Capture CIS , Capture-CIS , property , hierarchical schematics , Allegro 16.5 , SPB , placement report , design , OrCAD , 16.5 , Design Entry , SPB16.5 , PCB Capture , Schematic , Allegro

Verification

Using a Linaro File System on the Cadence Virtual Platform for the Xilinx Zynq-7000…

Linaro has emerged as a great place to find well tested toolchains, Linux kernels…

jasona 21 Feb 2012 • 3 min read

Verification

DVCon 2012 Preview: Focus on Formal & ABV Events and Papers

In a few short weeks DVCon 2012 will be upon us ( Feb. 27 - March 1 in San Jose …

TeamVerify 14 Feb 2012 • 2 min read

Joe Hupcey III , ABV , verification strategy , Functional Verification , Formal Analysis , ABVIP , Bin Ju , video , tutorial , Facebook , Chris Komar , DVcon , apps , assertion synthesis , assertions , robot , IEV , Assertion-Driven Simulation , Darrow Chu , Formal verification , IFV , Assertion-based verification

System, PCB, & Package Design

What's Good About ADW’s Server Metrics? Check out the 16.5 Release and See!

The Allegro Design Workbench (ADW) 16.5 has the capability of providing usage metrics…

Jerry GenPart 14 Feb 2012 • 1 min read

PCB , data management , usage metrics , Allegro Design Workbench , Library flow , server metrics , Team design , Allegro 16.5 , SPB , LRM , design data management , configuration manager , design , Library Revision Manager , PCB design , SPB16.5 , metrics , library , ADW

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