Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Cadence Japan

【ホンダHGR＋ケイデンス前編】Physical AIの“Physical”とは何か─現実に勝てないAIは、動けない

※本記事は、Honda総合研究センター/HGRに掲載された記事を、同社の許諾を得て転載しています。 皆さん、こんにちは。HGRセンター長の小川厚（おがわ あつし…

Cadence Japan
• less than a min read
featured , japanese blog

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Digital Design

Three Reasons to Move to EDI System 9.1

We recently announced the 9.1 version of the Encounter Digital Implementation System…

• 1 min read
Foundation Flow Design Closure , Encounter Digital Implementation System 9.1 , Digital Implementation , EDI system Encounter Digital Implementation System

System, PCB, & Package Design 

Come See TeamAllegro at DesignCon2010

A new year means another DesignCon and 2010 is an exciting year for the PCB and IC…

• 1 min read
SiP , Signal Intregrity , Allegro 16.3 , IBIS-AMI , PCB design , Desigcon

Verification

How Big Is An int?

This week I'm taking a break from my series on Android System Verification to talk…

• 8 min read
Small Device C Compiler , wishbone , z80 , OpenCores , ISX

Verification

Low-Power Verification With SystemC - The Great Unknown

Design teams have used C/C++/SystemC reference models for many years and the trend…

• 1 min read
Functional Verification , CPF , Low-Power , UPF , SystemC , IES , ESL

Verification

A Look Back On 2009 (Before Hazarding Predictions For 2010)

Before I gaze into a crystal ball and add to the many fine predictions already made…

• 3 min read
SystemVerilog , metric driven verification (MDV) , Functional Verification , C , EDA , e , multi-language , coverage driven verification (CDV) , SystemC , MDV , ESL

System, PCB, & Package Design 

What's Good About SiP Layout ADRC? See For Yourself Using The SPB16.3 Release!

In the SPB16.3 release, the SiP Layout Assembly Design Rules Checker (ADRC) User…

• 16 min read
SiP , DRC , SPB 16.3 , ACSET , ADRC , PCB design

Verification

Why UVM Does Not Equal OVM Plus VMM

In the numerous tweets, blog posts, and online forum discussions on the upcoming…

• 1 min read
uvm , methodology , Functional Verification , OVM , compatibility , Accellera , OVM 2.1 , VMM

Verification

Methodology Is Important But Language Matters - Part 1

Historical trends in languagesMany of us have traveled around the world, and while…

• 3 min read
Verification planning and management , TLM , virtual platform , System Design and Verification , ESL High Level Synthesis , OVM , ASIC/ASSP , ANSI-C , C-to-Silicon , virtual prototype , C program , OSCiI , TLM 2.0-driven design , planning and management , ESL

SoC and IP

The Evolving Enterprise SSD: Gartner’s Forecasts

By Steve Leibson for Denali Software The appearance of SSDs into the storage…

• 5 min read

SoC and IP

SSD Interfaces and Performance Effects

By Steve Leibson for Denali Software IDC ’s Research Director John Rydning…

• 4 min read

SoC and IP

SSD and HDD Economic Forecast: Analyst Jim Handy Speaks Out

By Steve Leibson for Denali Software If you’re waiting for solid-state drives…

• 3 min read

Verification

Scalability Made OVM The Ideal Choice For UVM

The popularity of OVM that made it the idea choice for Accellera's UVM is rooted…

• 1 min read
performance , SystemVerilog , uvm , OVM ML , Functional Verification , OVM , e , Simulation acceleration , MDV

Analog/Custom Design

Things You Didn't Know About Virtuoso: Options? What Options?

Recently, I got involved in helping out a customer who had become frustrated using…

• 1 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , IC 6.1.4 , Custom IC Design

Verification

Q&A With Nick Heaton: Accelerating Verification Methodology and Tool Adoption

TeamMDV: Have you ever wondered why EDA Vendors don't make it easier for our customers…

• 5 min read
workshops , IPCM , methodology , Verification methodology , metric driven verification (MDV) , Functional Verification , Incisive , Enterprise Manager , Plan and metrics management , MDV

Verification

Tech Tip: Waving Specman Objects in SimVision

Did you know that you can wave Specman objects in IES-XL *and* also save the wave…

• 1 min read
Specman , debug , Functional Verification , simvision , e , IES-XL

SoC and IP

The End of NAND Flash as we Know It: Micron’s Dean Klein and Samsung’s Tony Kim Look…

By Steve Leibson for Denali Software Today, NAND Flash is king of the semiconductor…

• 3 min read

Digital Design

Encounter Screencast: Editing Wires More Quickly With Bindkeys

The Encounter Digital Implementation System offers interactive wire editing capabilities…

• 1 min read
Wire Editor , encounter digital implementation system , Digital Implementation , bindkeys

System, PCB, & Package Design 

What's Good About SigXp UI Changes? SPB16.3 Has Many New Enhancements!

The SPB16.3 SigXP UI has been enhanced to focus on giving users better access to…

• 8 min read
SigXP UI , layer stacks , SPB 16.3 , PCB design , Allegro

Digital Design

Sometimes It's The Little Things: Working With Square Brackets in Encounter

Good news! A long-standing source of irritation for Encounter users has been addressed…

• 1 min read
Ease of Use , Encounter Digital Implementation System 8.1
CDNS - Fix Layout Hompage