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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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Blog - Post List
Latest blogs

Verification

Using wreals to Simulate Frequency Scaling for Dynamic Power Reduction

Some background info: Taking a quick look at Power dissipation in CMOS: …

• 3 min read
Low Power , Real Value Modeling , Functional Verification , Advanced Node , wreals , Mixed-Signal , Signal Integrity , verification

SoC and IP

Low-Power Memory Subsystems Imperative

The figure below was put forth at the recent Denali MemCon, in a speech by Samsung…

• 6 min read

Verification

AOP Discussion on LinkedIn

Hello All, Last week over in the LinkedIn Design Verification Professionals group…

• 3 min read
Specman , Functional Verification , OVM , e , AOP

Digital Design

Using A Dual Flop Methodology for Dynamic Power Savings

Imagine this scenario: Your chip is a low power design. You’ve used everything in…

• 1 min read
Low Power , dual flop , Digital Implementation

Analog/Custom Design

Things You Didn't Know About Virtuoso: The View From Above

A few years ago I bought a wonderful book called "Earth From Above". An amazing French…

• 2 min read
Virtuoso IC 6.1.3 , Virtuoso Layout Suite L , Virtuoso , VLS L , Custom IC Design

SoC and IP

Denali MemCon: Huge Hit in a Tough Market

Denali's 2009 Edition of MemCon, its Annual Storage and Memory-Only Conference held…

• 6 min read

Verification

Cadence System Design and Verification at DAC 2009

Traditionally in Cadence Marketing there were always two major events you really…

• 5 min read
DAC , System Design and Verification , schedule , C-to-Silicon , ESL handoff , SystemC , ARM

Verification

Another New Blog on e/Specman

Specmaniacs rejoice: there is a new blog centered around verification with e /Specman…

• less than a min read
IEEE 1647 , Specman , Functional Verification , e , OVMWorld

Verification

Industry Standard SystemC is What Designers Want

This past Monday saw not one HLS related announcement but two...this space is really…

• 2 min read
ANSI-C , C-to-Silicon , SystemC , HLS , System Design and Verification

Verification

Inside Cadence: Food for Charity & Freedom

Earlier today at the Cadence San Jose campus, a charity event was held off-cycle…

• 2 min read
Functional Verification , festival , Stars&Strikes , charity benefit

Digital Design

Flow? What Flow?

For EDA software, it seems that it takes just as much effort to develop a methodology…

• 1 min read
Foundation Flow , EDI system , encounter digital implementation system , Digital Implementation , design closure

System, PCB, & Package Design 

What's Good About USB 3.0? You Tell Me

I read a recent article (June 11, 2009) in EDN magazine - " USB 3.0: A simple Idea…

• 2 min read
USB 3.0 , PHY , PCB design

Verification

Demo: New Simulation Comparison Utility in Incisive Enterprise Simulator

When I first hired on as an AE at Cadence (eighteen years ago!), I realized how many…

• less than a min read
funtional verification , Functional Verification , simvision , Incisive , Incisive Enterprise Simulator (IES) , IES , verification , IES-XL

Analog/Custom Design

Things You Didn't Know About Virtuoso: Which Way Should I "Go"?

Just a short post this week, as I've been quite busy recording videos for some of…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

DAC Virtual Platform Workshop

Back in early May, I wrote that it was Not Too Early to Start Thinking About DAC…

• 1 min read
DAC , virtual platform , embedded software , metric-driven verification

RF Engineering

Periodic Steady-State Analysis for DC-to-DC Converters

In " Spectre RF by any other name ...", a non-RF application for Spectre RF's periodic…

• 3 min read
DAC , shooting newton , Spectre RF , THD , DC-to-DC converters , RF design , pss , SFDR

Verification

Create a Sine Wave Generator Using SystemVerilog

Two capabilities in SystemVerilog allow for the creation of a module that can produce…

• 2 min read
SystemVerilog , AMS , Functional Verification , Incisive , Incisive Enterprise Simulator (IES) , IES , IES-XL

SoC and IP

DDR3 DRAMs Update in June 2009

Abstract: DDR3 DRAMs, after a long period of floundering about, wondering 'when they…

• 3 min read

Verification

Yikes - Synopsys is Following Me!

No, I'm not being paranoid -- Synopsys, my largest competitor, is literally following…

• 2 min read
Specman , Functional Verification , OVM , OVM e , Coverage-Driven Verification , CDV , e , Twitter , eRM
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