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Cadence Japan

【ホンダHGR＋ケイデンス前編】Physical AIの“Physical”とは何か─現実に勝てないAIは、動けない

※本記事は、Honda総合研究センター/HGRに掲載された記事を、同社の許諾を得て転載しています。 皆さん、こんにちは。HGRセンター長の小川厚（おがわ あつし…

Cadence Japan
• less than a min read
featured , japanese blog

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

Verification

UVM = OVM 2.1: Even Better!

Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face…

• 1 min read
uvm , Functional Verification , OVM , Accellera VIP TSC

Verification

Built-in Message Logging – Part 1 of 2

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the…

• 2 min read
Specman , Functional Verification , tech tips , e , AOP , IES-XL

System, PCB, & Package Design 

What's Good AMS Simulator’s Probing? Check Out The SPB16.3 Release!

You'll need to check into the nifty new probe capabilities in the SPB16.3 Allegro…

• 1 min read
AMS , AMS simulator , SPB 16.3 , PCB design , Allegro

Digital Design

Signoff-Driven Implementation = Consistent and Convergent = Predictable and Effi…

Digital designs are reaching 10's of millions of instances, which makes efficiency…

• 2 min read
timing system , dynamic rail analysis , Static timing analysis , Early Rail Analysis , Multi-Core and Parallel rocessing , Statistical , Extraction , Signoff Analysis , timing constraints , SI analysis , noise analysis , OCV , Signal Integrity , Digital Implementation , Timing analysis , Power Analysis , signoff , timing convergence

Analog/Custom Design

Things You Didn't Know About Virtuoso: IC 6.1.4 ADE Enhancements

I'm not going to beat around the bush here. I could tell you about all the things…

• 2 min read
Virtuoso Analog Design Environment , Virtuoso , IC 6.1.4 , Custom IC Design

Verification

VIP Portfolio Extension: New AMBA 4 Protocol Support

ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing…

• 1 min read
metric driven verification (MDV) , Functional Verification , vPlan , Cadence VIP portfolio , OVM , VIP , Compliance Management System , CMS , AMBA , ARM

Verification

Have You Considered e Lately?

Richard Goering's recent interview with Mitch Weaver on the future of Specman and…

• 2 min read
SystemVerilog , Specman , Testbench simulation , e , verification

Verification

Running Incisive on Ubuntu Linux

Ubuntu is by many accounts the most popular and the easiest to use Linux distribution…

• 4 min read
Incisive , Ubuntu , Systemm Design and Verification , Virtual Machine , linux

System, PCB, & Package Design 

What's Good About Capture’s Auto-Wiring? You’ll Need The SPB16.3 Release to See!

Just a brief post this week to highlight one of the new SPB16.3 features in Allegro…

• 3 min read
Design Entry CIS , SPB 16.3 , Auto-wire , PCB design , Allegro

Verification

Why OOP Falls Short For Verification

Last week at DVCon , frequent Team Specman guest blogger Matan Vax of R&D gave a…

• less than a min read
Object Oriented Programming , Functional Verification , e , DVcon , OOP , Aspect Oriented Programming , AOP

Analog/Custom Design

Things You Didn't Know About Virtuoso: Thumbnails

Boy, you must think we're a few sandwiches short of a picnic over here at Cadence…

• 1 min read
IC 6.1 , thumbnails , Virtuoso , IC 6.1.4 , Custom IC Design

Analog/Custom Design

Analog Behavioral Modeling - What Language Do You Speak?

An increasing number of mixed-signal design teams are contemplating adding analog…

• 2 min read
mixed-signal simulators , MMSIM , analog , Mixed-Signal , Block-level simulation , AMS simulation , Circuit Design , mixed signal , Custom IC Design , Custim IC Design , Cusstom IC Design

Verification

DVCon 2010 - Day 3

Click here or on the image below to go to the annotated photo blog of DVCon 2010…

• less than a min read
Object Oriented Programming , Functional Verification , OVM , OVM e , OVM SV , DVcon , OOP , AMIQ , OVM SC

Verification

DVCon 2010 Rocked!

I've spent much of this week at the San Jose Doubletree Hotel for DVCon 2010 , and…

• 1 min read
DAC , uvm , methodology , Functional Verification , OVM , DVcon

Verification

DVCon 2010 - Day 2

Click here or on the image below to go to the annotated photo blog of DVCon Day 2…

• less than a min read
Functional Verification , OVM , OVM e , CDV , OVM SV , e , Mike Stellfox , DVcon , OOP , AOP

System, PCB, & Package Design 

What's Good About The Latest Cadence Online Support? Check Out This List!

This past weekend, several new enhancements and features were added to Cadence Online…

• 2 min read
Allegro Design Entry , SPB 16.3 , Support , Allegroro , PCB design

Digital Design

Encounter How To: Writing To/Reading From a File With TCL

A couple weeks ago, there was a good thread in the Digital Implementation Forums…

• 2 min read
EDI system , encounter digital implementation system , Digital Implementation , Closure , Foundation Flow Design , scripting , tcl

Verification

DVCon 2010 - Day 1

Click here or on the image below to go to the photo blog of DVCon Day 1. …

• less than a min read
uvm , Functional Verification , OVM , OVM e , OVM SV , DVcon , AMIQ , Accellera , OVM SC

Verification

DVCon "Day 0" - Quick Report From SystemC Day

If you were looking for more evidence that the transition from RTL to ESL is gaining…

• 1 min read
TLM , Functional Verification , DVcon , SystemC , System Verification , ESL
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