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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Analog/Custom Design

IC Design vs. Manufacturing Objectives - Can Both Be Achieved Concurrently?

IC designers and foundries typically have different objectives. IC designers want…

• 3 min read
Chip finishing , Virtuoso Space-based Router , Physical placement and layout , Virtuoso IC 6.1.3 , IC 6.1.4 , Custom IC Design , custom design technology

Verification

Performance-Aware e Coding Guidelines – Part 3

The constraint solver is a powerful and fun to use tool. Actually, it is so much…

• 1 min read
performance , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES , IES-XL

Digital Design

Constraint Construction: What's Its Function? Part 4 of 4

This is the last in the series of Constraint Construction blogs ! Today we're going…

• 2 min read
design rules , encounter , rtl compiler , Digital Implementation , modes of operation

System, PCB, & Package Design 

What's Good About DEHDL-CM Physical and Spacing Constraints? You'll need SPB16.2

That's right - the SPB16.2 release now includes support for Physical and Spacing…

• 2 min read
16.01 , SPB 16.2 , DEHDL , Design Entry HDL , PCB design , Allegro

Verification

Homeschoolers Hungry for Technology

Over the weekend I attended the 2009 Minnesota Homeschool Conference in downtown…

• 4 min read
System Design and Verification , Lego , mindstorms NXT

Digital Design

Encounter Digital Implementation System 8.1 San Jose Live Blog

I'll be live blogging from the Cadence Campus in San Jose today. We're doing a seminar…

• less than a min read
Low Power , encounter , Digital Implementation , mixed signal , design closure , Encounter Digital Implementation System 8.1

Verification

Tracing TLM 2.0 Activity in an ESL Design – Part 2

In my last post I discussed two ad hoc approaches for tracing TLM 2.0 activity in…

• 4 min read
System Design and Verification , TLM 2.0 , George Frazier , SystemC , TLM 2.0 Trace

Verification

Another New Blog About the e Language

We are compelled to briefly interrupt Efrat's excellent series on Performance-Aware…

• less than a min read
IEEE 1647 , Specman , Functional Verification , e , OVMWorld

Verification

Verification of AUTOSAR Software Using a SystemC Virtual Platform

[Please welcome ISX R&D team member Markus Winterholer back to the Team ESL blog…

• 2 min read
AUTOSAR , BSW , System Design and Verification , RTE , SystemC , VFB , ISX

Verification

ESC and "Booth-Centric" vs. "Paper Centric" Shows

Last Wednesday I walked the floor of the Embedded Systems Conference (ESC) , with…

• 2 min read
events , DAC , CDNLive , Functional Verification , ESC , DVcon

Verification

Performance-Aware e Coding Guidelines – Part 2

Building on Part 1 where I talked about the “do’s and don’ts” of List performance…

• 2 min read
performance , IntelliGen , Specman , Functional Verification , tech tips , OVM e , e , OVM-e , specman elite , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Analog/Custom Design

Virtuoso, the SATs, and the Dark Knight - Part II

Well, are you still wondering what Virtuoso has to do with the SATs and The Dark…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Observations From the Embedded Systems Conference

Yes, there was another Embedded Systems Conference this year. Several "multi-year…

• 2 min read
Embedded Systems Conference , RTL , System Design and Verification , ESL

Verification

EDN's 19th Annual Innovation Awards

Two of Cadence system D&V products have been selected as the finalists for the EDN…

• 1 min read
System Design and Verification , Palladium , EDN , dpa , C-to-Silicon Compiler

Verification

C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

Some customers have inquired if C-to-Silicon Compiler (CtoS) is a “Low Level” Synthesis…

• 1 min read
High-Level Synthesis , CTOS , TLM , high-level synthesis adoption , RTL , System Design and Verification , TLM 2.0 , C-to-Silicon , SystemC , C-to-Silicon Compiler , ESL , architect

Analog/Custom Design

Connectivity and Constraint Driven Design: Will It Ever Become The Standard for Custom…

In the late 70's and early 80's system level PCB and Digital IC physical design evolved…

• 6 min read
VSR , Virtuoso IC 6.1.3 , Virtuoso Custom Placer , CAD , IC 6.1.4 , Custom IC Design , custom design technology , VCP

System, PCB, & Package Design 

What's Good About Schematic Drawing Standards?

This past week, there has been a very interesting discussion on the "icu-pcb-forum…

• 2 min read
PTF , PCB design , Schematic , Allegro

Verification

Is ESL changing EDA? Absolutely!

Geoffrey James's recent article provides a succinct description of several important…

• less than a min read
DAC , Estimation Planning , TLM , RTL , System Design and Verification , Synthesis , ESL

Verification

Performance-Aware e Coding Guidelines - Part 1

[Team Specman welcomes back Methodology R&D leader Efrat Shneydor to present a 5…

• 1 min read
IEEE 1647 , performance , IntelliGen , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES-XL
CDNS - Fix Layout Hompage