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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Day 2 of CDNLive San Jose 2008

Highlights of Day 2: more great papers (with enough customer papers on OVM fill almost…

• less than a min read

System, PCB, & Package Design 

CDNLive! 2008 - San Jose: Day 3 ... Product Roadmaps, More Presentations, and Poker…

From the floor of CDNLive! 2008 - San Jose Each day continues to show the value that…

• 2 min read
CDNLive! 2008 , PCB design

Verification

Day 1 of CDNLive San Jose 2008

Suffice to say, Day 1 was quite a full day, with the highlight for me being some…

• less than a min read
AMS , CDNLive San Jose 2008 , Multi-domain verification: HW/SW co-verification , multi-language

System, PCB, & Package Design 

CDNLive! 2008 - San Jose: Day 2 ... Welcome, Keynote Speakers, Presentations

From the floor of CDNLive! 2008 - San Jose Wow! What an exciting, power packed, and…

• 1 min read
CDNLive! 2008 , PCB design , Michael Catrambone

Verification

Enterprise Verification gets a boost (a big one!)

Today we announced important new metric-driven verification capabilities in our enterprise…

• less than a min read
Verification methodology , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , CDV , Enterprise Manager , Plan and metrics management , coverage driven verification (CDV) , IES

Verification

"Day 0" of CDNLive San Jose 2008

Quick report from CDNLive Day 0 (I've labeled it that since this initial day was…

• 1 min read
CDNLive San Jose 2008 , MDV techtorial , System Verification

Verification

CDNLive SJ - system design and verification - don't miss it

If you are a system validation/verification engineer, an architect, a power engineer…

• 1 min read
Low Power , power engineer , system validation/verification engineer , embedded SW engineer , architect

System, PCB, & Package Design 

CDNLive! 2008 - San Jose: Day 1 ... from the Techtorials!

From the floor of CDNLive! 2008 - San Jose The first day, is always considered the…

• 1 min read
PCB Layout and routing , CDNLive , DEHDL , SPB16.2 , Design Entry HDL , ASA , Allegro System Architect (ASA) , Front-end PCB design , PCB design , CDNLive! , Allegro PCB Editor , ConceptHDL

Digital Design

Need for dynamic IR drop analysis at floor and power planning stages?

Here is a question for all the power grid designers out there: Do you see the need…

• 1 min read
dynamic rail analysis , Early Rail Analysis , Cadence Encounter Power System , Digital Implementation

Analog/Custom Design

CDNLive Techtorials: Everything you wanted to know about Virtuoso

Hey folks, if you are coming to the CDNLive conference, we have a lot of great "techtorials…

• less than a min read
RF design , CDNLive Techtorials , custom design technology

Verification

See you at CDNLive San Jose next week

FYI, Mike Stellfox and I will be at CDNLive San Jose next week. In addition to reporting…

• less than a min read
Functional Verification , OVM , ISX (Incisive Software Extensions) , IES

Verification

Chip Level Verification with Processors

Today, I will discuss some alternatives for chip-level verification with designs…

• 6 min read
verification strategy , Functional Verification , ISX , ARM , FPGA: DMA

Digital Design

Effectively communicating Low-Power and Power-Efficient Design knowledge

For those of you interested in the Power space I recently had an article published…

• less than a min read
Low-Power , Power-Efficient Design , Logic Design , Digital Implementation

RF Engineering

Tip of the Week: When should I use the pss/qpss Harmonic Balance vs. Shooting Newton…

Shooting Newton (shooting) and harmonic balance (HB) are complementary technologies…

• less than a min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design , Circuit Design

Digital Design

Demo: Interactive Floorplanning in SoC-Encounter

In this demonstration, we'll show how to perform the following actions: Resize a…

• less than a min read
SoC-Encounter , screencast , Rectilinear Cut , Floorplanning and Prototyping

System, PCB, & Package Design 

What's good about memristors? Who is planning on using them?

I recently read an interesting article in the August 18, 2008 Electronic Engineering…

• 1 min read
memristors , PCB design , Electronic Engineering Times

Verification

The Road to Better Software Verification

It seems the debate over the benefits of better software verification is still alive…

• 5 min read
Intel , Specman , System Design and Verification , Frank Schirrmeister

Digital Design

Demo: How To Make Multiple Edits with "Apply All" in SoC-Encounter

Today, I'm starting what I hope will be a series of screencasts where I demonstrate…

• less than a min read
SoC-Encounter , screencast , Digital Implementation , Apply All , Attribute Editor

RF Engineering

Tip of the Week: Guidelines for simulating oscillators - phase noise simulations

When simulating oscillators, it is important to choose the correct simulator engine…

• 2 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator XL , Spectre , RF design
CDNS - Fix Layout Hompage