Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

RF Engineering

Tip of the Week: Guidelines for simulating oscillators - phase noise simulations

When simulating oscillators, it is important to choose the correct simulator engine…

• 2 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator XL , Spectre , RF design

Verification

ESL: The state of the industry and what’s next?

While ESL continues to remain in its infancy, there are signs within the industry…

• less than a min read
System Design and Verification , ASIC/ASSP , advanced process nodes , ESL

System, PCB, & Package Design 

Analog/RF chip designers don't care about the Package?

So I have an observation that I would your thoughts/input on. On several occassions…

• less than a min read
Analog and RF SiP design , Analog chip design , IC Packaging & SiP design , Virtuoso , IC Package Physical layout and co-design , design chain

Verification

Experiences on Marketing a Verification Library

Inspired by JL Gray of the blog "Cool Verification" who stated, in this post: "I…

• 2 min read

System, PCB, & Package Design 

How stable is your IC Package's PDN?

There are three goals for a power a delivery network (PDN): sufficiency, efficiency…

• less than a min read
PDN , CDNLive , SPB , SPB16.2 , SerDes , SSN , DDR3

Verification

Embedded Systems Conference Boston 2008

Friday is that last day to get the Early Bird price for the Embedded Systems Conference…

• 1 min read
System Design and Verification , Coverage Driven Verification for Embedded Software , Embedded Systems Conference 2008 , debugging , Jason Andrews , verification

System, PCB, & Package Design 

Techtorials, Demos, Roadmaps ... Poker?

What do these 4 have in common? CDNLive! 2008 San Jose - September 8 - 11, 2008.…

• 2 min read
PCB Layout and routing , CDNLive , DEHDL , OrCAD Capture , PCB Signal and power integrity , Capture CIS , Library and design data management , SPB , High-Density Interconnect , Design Entry HDL , ASA , Allegro System Architect (ASA) , Front-end PCB design , PCB design , AMS simulation , Allegro PCB Editor , Differential Pair Support , ConceptHDL , SPB16.01 , OrCAD PCB Editor , HDI

Digital Design

Understanding Clock Net Markings in SoC-Encounter

I'm happy to report that the Digital Implementation Forums are picking up momentum…

• 3 min read
dbGet , Digital Implementation forums , CTE-TCL , encounter , clocks , saveClockNets

System, PCB, & Package Design 

Breaking down the 'virtual' wall

In the last 3-4 months I have seen, and been involved in, a flurry of discussions…

• 1 min read
IP , cadence , Allegro 16.2 , IC Packaging & SiP design , wirebond profile library , Kulicke & Soffa

System, PCB, & Package Design 

Verifying multi-technology chips-in-a-SiP, fact or fiction?

With everyone talking about System-in-Package (SiP), one challenge that often gets…

• less than a min read
Analog and RF SiP design , IC Packaging & SiP design , IC Package Physical layout and co-design

Verification

iPhone 3G issues - result of HW/SW-co-verification?

In a recent article at cnet, financial analyst said he believes Apple's iPhone 3G…

• 2 min read
Richard Windsor , Infineon 3G chipset , Infineon , System Design and Verification , iPhone 3G , Nomura

Verification

ESL gets a new taker

Interesting High-Level Synthesis review by Bryon Moyer at IC Design and Verification…

• less than a min read
High-Level Synthesis , IC Design and Verification , CDNLive! Silicon Valley 2008

RF Engineering

Tip of the Week: New nport parameter ( dcextrap ) for modeling longer transmission…

There is a new nport parameter, dcextrap, available in MMSIM 6.2.1. The values are…

• 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

System, PCB, & Package Design 

SPB 16.2 release - Constraint Driven HDI PCB Design Flow

Today's SPB 16.2 release is significant for the Cadence Allegro and OrCAD families…

• 3 min read
PCB Layout and routing , NVIDIA , Harris , High-Density Interconnect , PCB design , Allegro PCB Editor , OrCAD PCB Editor , HDI

Verification

Is Concurrent Engineering actually getting worse?

Today I'm taking a few minutes to jot down a few recent observations about the state…

• 3 min read
Concurrent Engineering , System Design and Verification , ISX

Verification

OVM - The Methodology for Enabling an Industry-wide VIP Eco-System

As the leader of the Cadence OVM development team, I was reading Richard Goering…

• 3 min read
SystemVerilog , OVM Professionals Network , Verification methodology , Functional Verification , Open Verification Methodology , OVM , Verification IP modeling , eRM , OVMWorld

System, PCB, & Package Design 

What's good about database parameters and XML import/export?

In the SPB16.01 release, you can now import/export database parameters from Allegro…

• 1 min read
PCB Layout and routing , XML import/export , SPB , PCB design , Allegro PCB Editor , SPB16.01 , OrCAD PCB Editor

RF Engineering

Simulating MOS Transistor ft

One other question that you might ask is, this approach works for bipolars but what…

• less than a min read
bipolar transistor , MOS transistor , RF design

System, PCB, & Package Design 

PartMiner Launches Unique Integration with Cadence OrCAD Capture

Cadence OrCAD Capture is integrated with PartMiner. As a long time EDA librarian…

• 1 min read
Steven Kamin , OrCAD Capture , PartMiner , PCB design
CDNS - Fix Layout Hompage