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The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

Verification

e Running Inside VCS Anniversary Updates?

It's been a year since I heard the first solid report about Synopsys supporting…

• less than a min read
IEEE 1647 , Specman , Testbench simulation , e , multi-language , Incisive Enterprise Simulator (IES) , IES

Digital Design

Tapeout!

With an early December tapeout looming, I've found myself too busy to write a post…

• 3 min read
ECO , LEC , DRC , LVS , Digital Implementation , Power Analysis , tapeout

System, PCB, & Package Design 

What's Good About Advanced Plating Bar Checks - Check out the SPB16.2 Release and…

New functionality has been added to the SPB16.2 Allegro Advanced Package Designer…

• 7 min read
SPB 16.2 , BGA , advanced package designer , advanced plating bar check , PCB design , Allegro

Verification

Virtualization and Verification With Posedge Software

Posedge Software is a Cadence Verification Alliance Member with skills in two of…

• 5 min read
posedge , open virtual platforms , System Design and Verification , OVP , QEMU

Verification

Thoughts on AMS Verification Inspired by the DV Club Lunch

Last week I had the pleasure of attending a DV Club lunch presentation from Dr.…

• 2 min read
AMS , verification strategy , Verification methodology , Functional Verification

System, PCB, & Package Design 

What's Good About HDI Via Structures - Check out the SPB16.2 Release and See!

New functionality has been added to the SPB16.2 Allegro PCB Editor suite of tools…

• 12 min read
SPB 16.2 , LMB , via , PCB design , microvia

Digital Design

Coming This Friday November 14th: SoC-Encounter Office Hours

I've really been enjoying the discussions in our Digital Implementation Forums…

• 1 min read
SoC-Encounter , Digital Implementation forums , chat

Digital Design

How to Change a Net Name

This is a question that comes up once every few months or so: "How do I change the…

• less than a min read
Digital Implementation

Digital Design

Demo: Partitioning a Design in SoC-Encounter

One of the longest standing capabilities in SoC-Encounter is its ability to partition…

• less than a min read
SoC-Encounter , partitioning , hierarchical design , screencast , Digital Implementation

Verification

Heads-up: Formal + Productivity Flow Technical Webinar Coming Up On Nov 12th

Heads-up: there is a free technical webinar next Wednesday 11/12 that goes deeper…

• 2 min read
FPV , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , CDV , Enterprise Manager , Plan and metrics management , coverage driven verification (CDV)

System, PCB, & Package Design 

What's Good About The SPB16.2 Release? WOW - Download It now!

The SPB16.2 release is now available (actually, it was available on 10/31/08 from…

• 2 min read
SPB 16.2 , PCB design , Allegro

Verification

Portable Design Names Cadence Incisive Palladium Dynamic Power Analysis its September…

In his article in Portable Design, John Donovan wrote: Palladium Dynamic Power Analysis…

• less than a min read
Portable Design , System Design and Verification , Palladium

Verification

Welcome Sharath Siddappa From Rambus, You Are The 5000th OVM World Registrant!

Welcome Sharath Siddappa, the 5000th OVM World registrant! In only 10 months, the…

• 1 min read
SystemVerilog , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , eRM , OVMWorld

Verification

OVM - The "O" Means Opportunity

A few months back I blogged that OVM was " Open for Business ". A nice play on words…

• 1 min read
Simantis , eclipse , KPIT , Functional Verification , IBM , Cadence VIP portfolio , OVM , Doulos

Verification

Report From the Advanced Verification Techtorial in San Jose Tuesday 10/28

I'm excited to report that Tuesday's techtorial, covering a range of topics underneath…

• 1 min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , techtorial

Verification

The Power of Cadence System Power Flow vs. Viewing from the Top

I feel that I must respond to the following blog published by Frank Schirrmeister…

• 6 min read
Incyte Chip , System Design and Verification , Incisive Enterprise Simulator , Palladium , power engineer , C-to-Silicon , Power Analysis , Frank Schirrmeister

Verification

ESC Boston: Day 2

This morning before heading to ESC it dawned on me that the park across the street…

• 4 min read
System Design and Verification , ESC , ISX , Coverage Driven Verification

Analog/Custom Design

Video Demo: ViVA-XL - Fast Waveform Viewing

It’s happened to each of us at some point in time. Your long simulation is finally…

• less than a min read
ViVa-XL , MMSIM , Simulators , Custom IC Design , Fast Waveform Viewing

System, PCB, & Package Design 

What's Good About Directive Locking?

Do you wish you could lock specific aspects of a DEHDL design content? Do you need…

• 5 min read
CPM Directive Control , DEHDL , Directive Lockhing , PCB design , SPB16.01
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