Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

RF Engineering: μWaveRiders: Cadence AWR Design Environment V16 Software Release Highlights

TeamAWR

The Cadence AWR Design Environment V16 production release is now available for download at Cadence Downloads with design environment, AWR Microwave Office, AWR VSS, AWR Analyst, and other enhancements.
- 23 Jul 2021
Computational Fluid Dynamics: This Week in CFD

John Chawner

Given that I'm perpetually late on sharing This Week in CFD here on the Cadence CFD blog, I ought to start calling it This Weekend in CFD or Last Week in CFD. But now that we're here... What does a DNS computation on 450,000 cores and a CFD...
- 23 Jul 2021
System, PCB, & Package Design : BoardSurfers: Accelerating Allegro Layout Tools Using NVIDIA GPUs for Complex Board Designs

pbernard

Boards and Packages are getting extremely complex and large; what used to be considered large with millions of objects is now close to 100s of millions of objects. Traditional rendering on CPU of such large and complex designs is not scalable for tod...
- 23 Jul 2021
System, PCB, & Package Design : BoardSurfers: Installation Know-How: Download Manager – Better than Ever Before

Shikha Jain

The Download Manager user interface has been revamped in 17.4-2019 HotFix 019. Various new features are integrated to enhance user experience and efficiency. The latest release of Download Manager delivers modern UI architecture with a scope for future enhancements...
- 23 Jul 2021
Computational Fluid Dynamics: Damen: Wind Study On A Slender Boat Design Using Computational Fluid Dynamics

AnneMarie CFD

DAMEN and Numeca develop a CFD methodology to proof a vessel has sufficient transversal stability to resist over-rolling in severe side winds. With more than 80 percent of the total global trade being transported through international ship...
- 23 Jul 2021
Breakfast Bytes: Machine Learning in EDA

Paul McLellan

Yesterday, in my post Cerebrus: The Future of Intelligent Chip Design, I talked about our latest product to use machine learning (ML) techniques to great effect. Although they are all slightly different, machine learning is also known as artificial i...
- 23 Jul 2021
System, PCB, & Package Design : Cadence OrCAD and Allegro 17.4-2019 HotFix SPB17.40.019 is Now Available

AllegroReleaseTeam

The HotFix 019 (QIR 3, indicated as 2021.1 in the application splash screens) update for Release 17.4-2019 of OrCAD and Allegro products is now available at Cadence Downloads. This blog post contains important links for accessing this update and introduces s...
- 22 Jul 2021
Breakfast Bytes: Cadence Cerebrus - Intelligent Chip Explorer

Paul McLellan

This morning, we announced the Cadence Cerebrus Intelligent Chip Explorer, a machine learning (ML)-based tool that automates and scales digital chip design. If you think about what a designer does with traditional EDA tools, a lot of it is running so...
- 22 Jul 2021
Life at Cadence: How Culture Can Flourish in the New Normal

Jaswinder

Peter Drucker rightly said, “Culture eats strategy for breakfast”. An inclusive high-performance culture is an enduring competitive advantage. We establish rituals and practices in the office, model desired behaviors, and lead by example...
- 21 Jul 2021
Breakfast Bytes: CadenceLIVE Cloud Panel

Paul McLellan

At the recent CadenceLIVE Americas, most of the sessions were pre-recorded with a live Q&A at the end. One exception to this was Big 3D FEM Simulations: Cloud or On-Prem? FEM stands for "finite element method" and is part of the te...
- 21 Jul 2021
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: Cadence Learning and SupportポータルのVirtuoso RF Solutionプロダクト・ページ

Custom IC Japan

Virtuoso Meets Maxwell はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC-パッケージ設計環境...
- 20 Jul 2021
カスタムIC／ミックスシグナル: Virtuoso Video Diary: LSCSジョブ制御モード - クラウド・シミュレーションを実現

Custom IC Japan

Virtuoso ADE Assemblerはアナログやミックスシグナルの設計のためシミュレーションを実行する、信頼されたツールとなっています。しかし、大量のシミュレーションを行うような状況では、次のようなことが必要になる場面を目にしたことがあるはずです：数日かかるシミュレーションを実行する必要があり、そしてその間、ICRPプロセスは何をしているのかと考えるジョブ数が増加したときにあらわれるdisplay/IO、その他ランダムなエラーを回避する必要がある設計検証のために数千のスイープ、コ...
- 20 Jul 2021
Verification: Comprehensive Approach to Verification of Interconnect-Centric Systems

DimitryP

Many of today’s SoCs are built around multi-layered, sophisticated interconnect IP components that link together multiple processor cores, caches, memories, and dozens of other IP blocks. These interconnects are enabling new generations of data servers and high-performance mobile devices. Being at the heart of SoCs, they introduce significant challenges to verification engineers both from functional verification and performance…
- 20 Jul 2021
Analog/Custom Design: Virtuosity: Making Optimum Use of Resources in Distributed Farm

Shyam Kumar Gupta

Details on a dedicated tab "Resources" in Job Policy form, which helps to do resource estimation while firing jobs in distributed farms like LSF, SGE, etc
- 20 Jul 2021
Breakfast Bytes: 75 Years of the Microprocessor

Paul McLellan

At the recent ISCA, there was a panel session with some of the major contributors to microprocessor development during the last 50 years. They were also asked to predict how they thought the microprocessor would develop during the next 25 years, goin...
- 20 Jul 2021
Verification: Why IDE Security Technology for PCIe and CXL?

Claire Ying

The new cloud, AI, Analytics, and Edge usage models with exponential data growth and connection drive the evolution of high-bandwidth PCIe (Peripheral Component Interconnect Express) version 5.0 and 6.0, CXL (Computer Express Link) version 2.0 and 3.0. Every component can be envisioned as an attack vector in modern computational systems, especially PCIe and CXL components, which are part of the system HW root-of-trust…
- 19 Jul 2021
Breakfast Bytes: Aerospace and Defense Systems Day...and DAU

Paul McLellan

Coming up on July 28 is CadenceCONNECT Aerospace and Defense Systems Day. Cadence experts will present on the most important issues facing teams in aerospace and defense (A&D). There is a common thread running through the presentations, namely ho...
- 19 Jul 2021
Breakfast Bytes: Sunday Brunch Video for 18th July 2021

Paul McLellan

https://youtu.be/nZ4lisR19nQ Made on my balcony (camera Carey Guo) Monday: Tesla Goes All-In on Vision...and Supercomputers Tuesday: 50 Years of the Microprocessor, Part 1 Wednesday: 50 Years of the Microprocessor, Part 2 Thursday: AWR: Int...
- 18 Jul 2021
PCB、IC封装：设计与仿真分析: 在云端运行 Clarity 3D Solver

SDA China

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“Bringing Clarity to the Cloud"。 space 今年5月，Cadence 推出了首款“混合云”产品 Clarity 3D Solver Cloud：将本地电脑端的Clarity 3D Solver和云端加速体验相结合，无需支付额外云计算费用。什么是“混合云”环...
- 16 Jul 2021
Computational Fluid Dynamics: This Week in CFD

John Chawner

Something weekend this way comes (to quote my online pal Brian who quotes Macbeth which reminds me it's been a long time since I had me a little Shakespeare). But I digress. It's time for the weekly round up of CFD news and events. Speaking ...
- 16 Jul 2021
Digital Design: Voltus Voice: Full-Chip Resistance Analysis – The Holy Grail of Power Grid Verification

bertrandgenneret

Do you want to determine the weak spots in your power grid network at the start of physical design? Then go ahead and read this blog to learn more about the different resistance analysis techniques to prevent a voltage drop and model a robust power grid.
- 16 Jul 2021
Breakfast Bytes: What Comes after 2nm GAA?

Paul McLellan

There are three companies that currently pursue the smallest geometries, what I've heard called "the race to the end of Moore's Law". One is based in Korea, one in Taiwan, and one in the US. So the obvious place to go to find out wh...
- 16 Jul 2021
System, PCB, & Package Design : BoardSurfers: Exchanging Manufacturing Data in IPC-2581 Format Using Allegro PCB Editor

vignesh k

IPC-2581 ensures efficient PCB design data transfer and brings advanced capabilities to extract all the required data for manufacturing and assembly. This includes netlist, test pad information, artwork, drill data, bill of materials, test files, and design variants. While exporting data, you can choose to suppress any information which is not needed for fabrication, assembly, testing, or procurement
- 15 Jul 2021
Breakfast Bytes: AWR: Intelligent RF Design

Paul McLellan

There is a new release of the AWR Design Environment with cross-platform workflows to support RF to mmWave based on both the Virtuoso (chip) and Allegro (PCB/package) platforms, and with integration to the system-level analysis solution Clarity ...
- 15 Jul 2021
System, PCB, & Package Design : Sigrity and Systems Analysis 2021.1 HF2 Release July Update Now Available

SigrityReleaseTeam

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2021.1 HF2 release is now available for download at Cadence Downloads. For the list of CCRs fixed in the 2021.1 HF2 release, see the README.txt file in the installation hierarchy.
- 14 Jul 2021

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.