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Verification: PSS2.0 is Out – Reflections on the Role of a Standard

matan

We all know that a common language is the basis for every collaborative activity. This is true of natural languages and formal languages alike. In engineering, and specifically in the domain of hardware design/verification, domain languages and forma...
- 21 Apr 2021
System, PCB, & Package Design : (P)SpiceItUp: Search by Category, Description, or Function with PSpice Part Search

Shailly

As a designer, your requirement at the early stages of schematic design is quite different, that is the part information you need when it comes to implementing the schematic design and while simulating it for testing and analysis is different i...
- 21 Apr 2021
Breakfast Bytes: Embracing a Zero Trust Security Model

Paul McLellan

A couple of months ago, the National Security Agency (NSA) published a document titled Embracing a Zero Trust Security Model. I wrote about this topic almost exactly a year ago in my post From Castles and Moats to Zero-Trust Networking. The prob...
- 21 Apr 2021
Breakfast Bytes: Brian Jackson Introduces a Mystery Product at IMAPS (Shh, It's OrbitIO)

Paul McLellan

I have been criticized in the past for calling OrbitIO the "red-headed stepchild" of the Cadence product line. I think I shall have to improve my positioning and simply call it "ahead of its time". OrbitIO is the cockpit for all t...
- 20 Apr 2021
Verification: CCIX Coherency: Verification Challenges and Approaches

DimitryP

Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the most complex challenges faced by verification engineers. Over the years, it became even more challenging with increasing number of cores in CPU clusters and introduction of the embedded L3 (level 3) cache to the coherent…
- 19 Apr 2021
Verification: PSS 2.0 Is Available and Driving Portable Stimulus to the Mainstream!

Moshik Rubin

Three years ago, PSS (Portable Test and Stimulus) specification 1.0 was released and started to reshape the way design and verification engineers think about SoC level verification and testing. It took a noble idea of creating a single repr...
- 19 Apr 2021
Breakfast Bytes: Update: Pointwise, PCIe, RISC-V

Paul McLellan

This is another of my occasional update posts, covering changes to recent posts that are not big enough to justify an entire post on their own. Today, Pointwise and PCIe. You will almost certainly have to read further to discover who Pointwise is. Yo...
- 19 Apr 2021
RF /マイクロ波設計: μWaveRiders:Cadence AWR ソフトウェアでの強化されたロードプル

RF Design Japan

　Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design Environmentのリリースのハイライト, 機能ビデオ, Cadenceの教育関係ネットワークのニュース,ソフトウェアのヒント, トリック, カスタマイズ, 機能のスポットライトの中で変わります。このシリーズの新しいブログに関する通知を受け取るために、Subscribe Nowをクリックし、Su...
- 18 Apr 2021
Breakfast Bytes: Sunday Brunch Video for 18th April 2021

Paul McLellan

https://youtu.be/afv9_fRCrq8 Made at Target Oakridge (camera Ziyue Zhang) Monday: "Targeting" the Open Compute Project Tuesday: NUMECA, Computational Fluid Dynamics...and the America's Cup Wednesday: Benedict Evans on Tech 2021: Harder ...
- 18 Apr 2021
Analog/Custom Design: Virtuoso Meets Maxwell: Creating Connectivity Between Die and BGA Package for IC Packaging Process

mgoode

Before the creation of die and package layout can begin, logical connectivity between these two fabrics need to be established. Based on the number of input or output and power or ground connections needed, the physical size and pin arrangement of the IC and package can start.
- 16 Apr 2021
RF Engineering: μWaveRiders: Enhancing Load Pull with Cadence AWR Software

TeamAWR

The Cadence AWR Design Environment platform V15 offers enhanced load pull capabilities that include an expanded harmonic balance tuner (HBTUNER3) and an updated load pull script for performing load pull analysis.
- 16 Apr 2021
Analog/Custom Design: Virtuosity: What’s New on the Cadence Learning and Support Portal – Virtuoso Layout Product Page

Dishika Majumdar

Cadence Learning and Support portal has introduced a new one-stop learning resource to guide you about different features of the Virtuoso Layout Suite products. Click here to know more.
- 16 Apr 2021
Spotlight Taiwan: Palladium Z2和Protium X2 雙重奏(Dynamic Duo)引擎系統、邁向驗證新時代 !

candyyu

原文出處: Dynamic Duo 2: The Sequel作者: Paul McLellan有一個故事，可能是虛構的，關於一位編劇在好萊塢找人投資影片的故事。考慮投資的製片說：“這看起來像一部很棒的電影，可惜的是沒有人拍過，所以我們未來可拍續集。”而正好最近幾乎所有其他電影似乎都是漫畫電影或《星球大戰》第47集的續集，所以這故事也許這不是虛構的。過去一年左右，我一直在談論Dynamic Duo。請參考我之前發表的文章 - 動力雙重奏(Dynam...
- 16 Apr 2021
Computational Fluid Dynamics: This Week in CFD

Paul McLellan

This Week in CFD reached convergence long before I had exhausted the two-week backlog of news. With baseball season underway here in the US, fans will enjoy the case study describing how high-fidelity CFD can predict the trajectory of various types o...
- 16 Apr 2021
Breakfast Bytes: Evolving Maturity in Ransomware

Paul McLellan

I recently attended a Black Hat seminar titled The Evolving Maturity in Ransomware Operations. It was scary. A high-level summary would be that ransomware has become more targeted, more professional, and more lucrative. I am using the word "prof...
- 16 Apr 2021
カスタムIC／ミックスシグナル: Spectre Tech Tips: リークパスによる電流ホットスポットの検出

Custom IC Japan

回路設計において、誤った接続が望ましくないリークパスを引き起こし、結果として電流のホットスポットとなる可能性があります。こういった電流のホットスポットはSpectre®のdynamicデザインチェックによって素早く特定することができます。このブログでは、リークパスによる電流ホットスポットの根本原因を特定するために、Spectreデザインチェックの使い方を記載します。デジタル設計における消費電流デジタルCMOS設計では、電源の消費電流は一般的にとても小さくなります。なぜなら、デジタル回...
- 15 Apr 2021
Computational Fluid Dynamics: AeroDelft Pushes the Airline Industry towards a Sustainable Future with Liquid Hydrogen Aircraft

Paul McLellan

AeroDelft is a student team at the forefront of sustainable aviation. While based in Delft, over forty students from different schools and universities around the Netherlands have joined together and are working hard to push the airline industry tow...
- 15 Apr 2021
Breakfast Bytes: Programming Early Computers Was Very Different from Today

Paul McLellan

In my post "I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a Car" I wrote about that quote from Agatha Christie. Today, when a flashlight app on your smartphone needs "only" 250KB, it is hard for peopl...
- 15 Apr 2021
Digital Design: Verifying Design Changes Does Not Have to be Difficult and Tedious — Make it Easier with Conformal Equivalence Checker

FormerMember

You put your design through a multitude of tools for various transformations.

Going back to formal verification in between every change to rely on your simulation tools can be a rigorous approach, but wait... there is an easier way: Use equivalence checking, with Conformal® Equivalence Checker.

And that easier way is made even easier with these videos on how to do your equivalence checking, along with a few of the…
- 14 Apr 2021
Breakfast Bytes: Benedict Evans on Tech 2021: Harder Problems and Regulation

Paul McLellan

This is a continuation of last week's post Benedict Evans' on Tech in 2021. That covered Covid Acceleration and the Great Unbundling. Today, the rest of his presentation. Harder Problems In the first 20 years of the inter...
- 14 Apr 2021
SoC and IP: First Look: Cadence Subsystem SoC for PCIe 5.0

Arif Khan

If a picture is worth a thousand words, a video tells you the entire story. Cadence's subsystem SoC silicon for PCI Express (PCIe) 5.0 demo video shows you how we put together the latest technology in TSMC's advanced FinFET technology to bring to market a compelling, low-power solution and tested it with the latest industry test solutions available.

https://youtu.be/Mgy5Z-sKs6E

The subsystem contains Cadence…
- 13 Apr 2021
定制IC芯片设计 : Virtuoso Video Diary: “Training bytes” 助推知识传播—第4部分

Parula

我们生活在一个日趋复杂的世界中，尽可能的使用和组合各种工具及平台，以及其它的可用功能，这对于我们而言至关重要. 在此博客中，我们将介绍如何使用Spectre Simulation 平台快速获得最优结果.
- 13 Apr 2021
System, PCB, & Package Design : BoardSurfers: Training Insights: Setting Up and Using Pin Delays in Constraint Manager

Niharika1

Pin delays are used to specify the time delay or length from the internal package connection to the pin’s mounting layer. It is critical to include pin delays when tuning high-speed nets to ensure signal performance. Pin delays are used in the ...
- 13 Apr 2021
System, PCB, & Package Design : Sigrity and Systems Analysis 2021.1 HF1 Release Now Available

SigrityReleaseTeam

The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2021.1 HF1 release is now available for download at Cadence Downloads. For the list of CCRs fixed in the 2021.1 HF1 release, see the README.txt file in the installation hierarchy...
- 13 Apr 2021
Breakfast Bytes: NUMECA, Computational Fluid Dynamics...and the America's Cup

Paul McLellan

What is computational fluid dynamics, or CFD? And what does that have to do with the America's Cup? This year it was won by Emirates Team New Zealand. Their secret weapon was NUMECA's FINE/Marine CFD software, which was used to design the hull and fo...
- 13 Apr 2021

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