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Breakfast Bytes: vManager: One Manager to Rule Them All

Paul McLellan

Here's a high-level view of verification: If everyone properly plans their verification project, why do quality problems and schedule slips persist? It really comes down to the adage “Begin with the end in mind.” A good plan contains...
- 23 Jun 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Full CellView EM Extraction

jgrad

This blog introduces the full cellview extraction feature of the Virtuoso RF Solution that allows you to extract a 3D S-parameter model for a complete layout cellview. Read more...
- 22 Jun 2020
定制IC芯片设计 : Virtuoso Meets Maxwell：了解您的举动–我们正在进行芯片、封装和电路板协同编辑

Steve PDK Lee

该博客介绍了Cadence Virtuoso RF 解决方案中的Edit-in- Concert 技术，它可以帮助设计师们查看和编辑die packages 及其相应的die 布局。
- 22 Jun 2020
Breakfast Bytes: Make a DATE for the Alps Next Ski Season

Paul McLellan

It's the Summer Solstice. To be precise, that was on Saturday, the longest day of the year, but Breakfast Bytes doesn't appear at weekends. Surprisingly, the earliest sunrise of the year was on June 13, a week ago. And the latest su...
- 22 Jun 2020
Breakfast Bytes: Sunday Brunch Video for 21st June 2020

Paul McLellan

www.youtube.com/watch Made in "cherry blossoms" (camera Carey Guo) Monday: IEEE 1838: Taking Test into the Third Dimension Tuesday: Uncanny Valley: Being Human in the Age of AI Wednesday: Fully Homomorphic Encryption Thursday: On Writi...
- 21 Jun 2020
Academic Network: Digital Design and Signoff Training Deep Dive: Part 2 – Implementation

Kira Jones

Welcome back to our series, and if you’re new here, thanks for joining us today! We’re going to be looking at another part of Digital Design and Signoff solutions: Implementation. We’ll be building off the recommended courses from o...
- 18 Jun 2020
Analog/Custom Design: Start Your Engines: Using CLIPS to Generate Portable Virtuoso IP for SoC Verification

Lalit Mohan

Mixed-signal functional verification is a complex task and it takes a lot of effort and multiple simulation cycles to verify a design correctly. A mixed-signal verification engineer works with the analog IP developers, digital design team, and modeling team in parallel.
- 18 Jun 2020
Breakfast Bytes: On Writing

Paul McLellan

Tomorrow is Juneteenth, which commemorates the ending of slavery in the United States. It is a Cadence holiday. Breakfast Bytes will not appear. Today's off-topic post is about how I became a writer. The short answer is "by accident" si...
- 18 Jun 2020
定制IC芯片设计 : Virtuosity: Automated Device Placement and Routing Flow 中的器件阵列

Sravasti

在此博客中，我将讨论该ADA功能如何成为新APR解决方案不可或缺的一部分。
- 17 Jun 2020
Breakfast Bytes: Fully Homomorphic Encryption

Paul McLellan

Do you know what Fully Homomorphic Encryption (FHE) is? When I first heard about it a few years ago, I thought it was something of minor academic interest, like those schemes for giving keys to a group where any 3 of them can decrypt the message but ...
- 17 Jun 2020
System, PCB, & Package Design : IC Packagers: Navigating Your Visible Design

Tyler

Last week we introduced you to the new dark theme. But, we listen to your suggestions for ideas of other ways to improve your ability to move around your design efficiently. That brings me to two other items which you have your peers in our loyal com...
- 16 Jun 2020
System, PCB, & Package Design : BoardSurfers: Training Insights: Creating High-Speed Via Structures

Shreyansh

High-speed via structures combine vias, connect lines (clines) or traces, static shapes without voids, and route keep-outs. High-speed via structures comprise of differential pairs with return path vias and route keep-outs for custom voiding.
- 16 Jun 2020
カスタムIC／ミックスシグナル: Start Your Engines: AMSD Flex—Take your Pick! – AMSD Flexモードの紹介

Custom IC Japan

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により、ミックスシグナル・デザイン検証を「活性化」し、市場競争でチェッカーフラッグを受けることができます。Start Your Enginesブログ・シリーズは、シミュレーションのパフォーマンスをチューンアップし、生産性向上に役立つヒントと洞察を提供します。 Start...
- 16 Jun 2020
Breakfast Bytes: Uncanny Valley: Being Human in the Age of AI

Paul McLellan

Today's post is somewhat off-topic, despite having AI in the title. Uncanny Valley: Being Human in the Age of AI is the name of an exhibition at the de Young Museum in Golden Gate Park in San Francisco. I went to see it before we got locked...
- 16 Jun 2020
Verification: Training Insights - Comprehensive RTL Signoff Using JasperGold Superlint App

Nizar Hanna

Most have heard the phrase "time is money". Thinking more about it, probably the right phrase would be "time is more valuable than money". People look at their bank accounts with great attention but don't tend to look at their time the same way, ending up wasting this greatly valuable and important resource. You can gain money using time, but you can’t use money to purchase more time.

The …
- 15 Jun 2020
Breakfast Bytes: IEEE 1838: Taking Test into the Third Dimension

Paul McLellan

I've written quite a bit recently about advanced packaging and More than Moore technologies for building systems. For example, see my posts: John Park's Webinar on Chiplets Known Good Die System in Package, Why Now? System in Package, Why No...
- 15 Jun 2020
Breakfast Bytes: Sunday Brunch Video for 14th June 2020

Paul McLellan

www.youtube.com/watch Made in Hakone Japanese Garden, Saratoga (camera Carey Guo) Monday: ETS2020: Functional Safety Tuesday: Take a Cadence Masterclass and Get a Badge Wednesday: Sophie Wilson: The 2020 Wheeler Lecture (The 6502 to Multicore) T...
- 14 Jun 2020
PCB、IC封装：设计与仿真分析: 极致PCB设计全流程 I 技巧四：巧用布局技巧

SDA China

多层板设计时，我们肯定都希望能一次性完成完整平面的设计、一次性消除密间距器件的DRC、一次性完成微孔+埋孔协同fanout……本期技巧篇内容将帮助我们轻松达成这些目的。微信后台回复关键词“PCB全流程”即可get完整课程计划与资料汇总页面链接，快快添加收藏吧~ 点击图片可查看清晰大图，点击此处下载PDF版完整内容 “极致PCB设计全流程网课计划”第四期实战直播识别下图二维码，立刻报名！相关内容 ...
- 13 Jun 2020
PCB、IC封装：设计与仿真分析: 极致PCB设计全流程 I 基础四：高质量快速布局

SDA China

布局布线是PCB设计的物理实现环节，在本期内容和接下来的第五期内容中，我们将聚焦于如何利用布局布线规划来减少重复劳动，提升设计效率，将有限的时间用在“刀刃”上。微信后台回复关键词“PCB全流程”即可get完整课程计划与资料汇总页面链接，快快添加收藏吧~ 点击图片可查看清晰大图，点击此处下载PDF版完整内容 “极致PCB设计全流程网课计划”第四期实战直播识别下图二维码，立刻报名！ sp...
- 12 Jun 2020
Life at Cadence: My Life at Cadence Video Series: Chaitra Dustker

Mary Kasik

Cadence recently interviewed five of our amazing women engineers for a new video series titled “My Life at Cadence”! This second video features Chaitra Dustker, lead applications engineer, Digital Implementation. I became interested in e...
- 12 Jun 2020
Breakfast Bytes: Custom Instructions in Tensilica: Wearing a TIE Makes You Smarter

Paul McLellan

Tensilica has a number of different product families targeted at different applications from audio, via video, to deep learning. I've written posts about all of these during the last year. The most recent in each domain were: Audio: HiFi D...
- 12 Jun 2020
System, PCB, & Package Design : Cadence OrCAD and Allegro 17.4-2019 HotFix 007 Is Now Available

AllegroReleaseTeam

The HotFix 007 (QIR 1, indicated as 2020 in the application splash screens) update for OrCAD and Allegro is now available at Cadence Downloads. This release includes many improved product features and new enhancements, mostly resulting from...
- 11 Jun 2020
Digital Design: Library Characterization Tidbits: Understanding the Liberate AMS Command-Line Flow

Jommy

Read to know about the Liberate AMS command-line flow.
- 11 Jun 2020
Breakfast Bytes: Sophie Wilson: The 2020 Wheeler Lecture (Multicore to Today)

Paul McLellan

This is the second post continuing from yesterday's post Sophie Wilson: The 2020 Wheeler Lecture (The 6502 to Multicore) covering Sophie Wilson's Wheeler Lecture from Cambridge in the middle of May. Here is the linkfest of the most rece...
- 11 Jun 2020
Learning and Support: Come Join Us for a SystemVerilog Real Number Modeling Seminar!

XTeam

Looking to improve your SystemVerilog? On June 17th, 2020, there’s a webinar going on at 9:00 CEST that can help you out. Come join us for our SystemVerilog Real Number Modeling seminar! You’ve been using device assertions and checks in y...
- 10 Jun 2020

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