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Latest Blog Posts

  • RF Engineering: μWaveRiders: Enhancing Load Pull with Cadence AWR Software

    TeamAWR
    TeamAWR
    The Cadence AWR Design Environment platform V15 offers enhanced load pull capabilities that include an expanded harmonic balance tuner (HBTUNER3) and an updated load pull script for performing load pull analysis.
    • 16 Apr 2021
  • Analog/Custom Design: Virtuosity: What’s New on the Cadence Learning and Support Portal – Virtuoso Layout Product Page

    Dishika Majumdar
    Dishika Majumdar
    Cadence Learning and Support portal has introduced a new one-stop learning resource to guide you about different features of the Virtuoso Layout Suite products. Click here to know more.
    • 16 Apr 2021
  • Spotlight Taiwan: Palladium Z2和Protium X2 雙重奏(Dynamic Duo)引擎系統、邁向驗證新時代 !

    candyyu
    candyyu
    原文出處: Dynamic Duo 2: The Sequel作者: Paul McLellan有一個故事,可能是虛構的,關於一位編劇在好萊塢找人投資影片的故事。考慮投資的製片說:“這看起來像一部很棒的電影,可惜的是沒有人拍過,所以我們未來可拍續集。”而正好最近幾乎所有其他電影似乎都是漫畫電影或《星球大戰》第47集的續集,所以這故事也許這不是虛構的。 過去一年左右,我一直在談論Dynamic Duo。請參考我之前發表的文章 - 動力雙重奏(Dynam...
    • 16 Apr 2021
  • Computational Fluid Dynamics: This Week in CFD

    Paul McLellan
    Paul McLellan
    This Week in CFD reached convergence long before I had exhausted the two-week backlog of news. With baseball season underway here in the US, fans will enjoy the case study describing how high-fidelity CFD can predict the trajectory of various types o...
    • 16 Apr 2021
  • Breakfast Bytes: Evolving Maturity in Ransomware

    Paul McLellan
    Paul McLellan
    I recently attended a Black Hat seminar titled The Evolving Maturity in Ransomware Operations. It was scary. A high-level summary would be that ransomware has become more targeted, more professional, and more lucrative. I am using the word "prof...
    • 16 Apr 2021
  • カスタムIC/ミックスシグナル: Spectre Tech Tips: リークパスによる電流ホットスポットの検出

    Custom IC Japan
    Custom IC Japan
    回路設計において、誤った接続が望ましくないリークパスを引き起こし、結果として電流のホットスポットとなる可能性があります。こういった電流のホットスポットはSpectre®のdynamicデザインチェックによって素早く特定することができます。このブログでは、リークパスによる電流ホットスポットの根本原因を特定するために、Spectreデザインチェックの使い方を記載します。 デジタル設計における消費電流 デジタルCMOS設計では、電源の消費電流は一般的にとても小さくなります。なぜなら、デジタル回...
    • 15 Apr 2021
  • Computational Fluid Dynamics: AeroDelft Pushes the Airline Industry towards a Sustainable Future with Liquid Hydrogen Aircraft

    Paul McLellan
    Paul McLellan
    AeroDelft is a student team at the forefront of sustainable aviation. While based in Delft, over forty students from different schools and universities around the Netherlands have joined together and are working hard to push the airline industry tow...
    • 15 Apr 2021
  • Breakfast Bytes: Programming Early Computers Was Very Different from Today

    Paul McLellan
    Paul McLellan
    In my post "I Couldn't Imagine Being Too Poor for Servants, or Rich Enough for a Car" I wrote about that quote from Agatha Christie. Today, when a flashlight app on your smartphone needs "only" 250KB, it is hard for peopl...
    • 15 Apr 2021
  • Digital Design: Verifying Design Changes Does Not Have to be Difficult and Tedious — Make it Easier with Conformal Equivalence Checker

    FormerMember
    FormerMember

    You put your design through a multitude of tools for various transformations.

    Going back to formal verification in between every change to rely on your simulation tools can be a rigorous approach, but wait... there is an easier way: Use equivalence checking, with Conformal® Equivalence Checker.

    And that easier way is made even easier with these videos on how to do your equivalence checking, along with a few of the…

    • 14 Apr 2021
  • Breakfast Bytes: Benedict Evans on Tech 2021: Harder Problems and Regulation

    Paul McLellan
    Paul McLellan
    This is a continuation of last week's post Benedict Evans' on Tech in 2021. That covered Covid Acceleration and the Great Unbundling. Today, the rest of his presentation. Harder Problems In the first 20 years of the inter...
    • 14 Apr 2021
  • SoC and IP: First Look: Cadence Subsystem SoC for PCIe 5.0

    Arif Khan
    Arif Khan

    If a picture is worth a thousand words, a video tells you the entire story. Cadence's subsystem SoC silicon for PCI Express (PCIe) 5.0 demo video shows you how we put together the latest technology in TSMC's advanced FinFET technology to bring to market a compelling, low-power solution and tested it with the latest industry test solutions available.

    https://youtu.be/Mgy5Z-sKs6E

    The subsystem contains Cadence…

    • 13 Apr 2021
  • 定制IC芯片设计 : Virtuoso Video Diary: “Training bytes” 助推知识传播—第4部分

    Parula
    Parula
    我们生活在一个日趋复杂的世界中,尽可能的使用和组合各种工具及平台,以及其它的可用功能,这对于我们而言至关重要. 在此博客中, 我们将介绍如何使用Spectre Simulation 平台快速获得最优结果.
    • 13 Apr 2021
  • System, PCB, & Package Design : BoardSurfers: Training Insights: Setting Up and Using Pin Delays in Constraint Manager

    Niharika1
    Niharika1
    Pin delays are used to specify the time delay or length from the internal package connection to the pin’s mounting layer. It is critical to include pin delays when tuning high-speed nets to ensure signal performance. Pin delays are used in the ...
    • 13 Apr 2021
  • System, PCB, & Package Design : Sigrity and Systems Analysis 2021.1 HF1 Release Now Available

    SigrityReleaseTeam
    SigrityReleaseTeam
    The Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2021.1 HF1 release is now available for download at Cadence Downloads. For the list of CCRs fixed in the 2021.1 HF1 release, see the README.txt file in the installation hierarchy...
    • 13 Apr 2021
  • Breakfast Bytes: NUMECA, Computational Fluid Dynamics...and the America's Cup

    Paul McLellan
    Paul McLellan
    What is computational fluid dynamics, or CFD? And what does that have to do with the America's Cup? This year it was won by Emirates Team New Zealand. Their secret weapon was NUMECA's FINE/Marine CFD software, which was used to design the hull and fo...
    • 13 Apr 2021
  • SoC and IP: Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0

    Arif Khan
    Arif Khan

    Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0 to the market and the lowest power 3.0 PHY at introduction. We're proud to continue the trend with our solution for PCIe 5.0 that continues to blaze the trail with new benchmarks for power, performance, and area.

    Figure 1: I/O Bandwidth doubling every three years and PCI Specification Updates


    The PCIe standard has been around for nearly…

    • 12 Apr 2021
  • Breakfast Bytes: "Targeting" the Open Compute Project

    Paul McLellan
    Paul McLellan
    Target (yes, that Target, the retailer) has an infrastructure and cloud conference, held last week. There CIO Mike McNamara (not to be confused with Cadence alumnus Michael "Mac" McNamara now CEO of Adapt-IP) announced that Target would joi...
    • 12 Apr 2021
  • Breakfast Bytes: Sunday Brunch Video for 11th April 2021

    Paul McLellan
    Paul McLellan
    https://youtu.be/D29rGqkkf80 Made in "Hawaii" (camera Ziyue Zhang) Monday: Dynamic Duo 2: The Sequel Tuesday: Gall's Law and Big Ball of Mud Wednesday: Benedict Evans on Tech in 2021 Thursday: Cadence/Samsung Automotive Reference F...
    • 11 Apr 2021
  • Breakfast Bytes: Have You Heard of ISO 21434? You Will

    Paul McLellan
    Paul McLellan
    You probably already know what ISO 26262 is. If you don't, then you can find out in several previous posts: "The Safest Train Is One that Never Leaves the Station" History of ISO 26262 ISO 26262...Chapter 11 What to Do About IP Developed Before ISO ...
    • 9 Apr 2021
  • PCB設計/ICパッケージ設計: Allegro System Capture のやり方で設計する

    SPB Japan
    SPB Japan
    ロジック設計エンジニアのためのシリーズ 洗練された新しい設計エコシステム、Allegro® System Captureの世界へようこそ。この ASCENT シリーズでは、Allegro System Captureとは何か、 部品登録やデザイン生成などレイアウトファイル作成につながるステップにおける様々な機能やフローをこのアプリケーションの中でどのように利用できるか、を探っていきます。  何よりもまず、あなたが抱いているかもしれない疑問について... &n...
    • 9 Apr 2021
  • Analog/Custom Design: Virtuoso Video Diary: Knowledge Booster - 5G mmWave Handset System Design

    Parula
    Parula
    In this blog we would like to let you know – amongst other things - how to implement a transceiver RFIC module of a 5G mmWave mobile handset working at 28GHz using the Cadence Virtuoso multi-technology framework.
    • 8 Apr 2021
  • カスタムIC/ミックスシグナル: Virtuoso Video Diary: Virtuoso Visualization and Analysis XLのTabular Graph

    Custom IC Japan
    Custom IC Japan
    読者の皆様、こんにちは。 今回は、Virtuoso Visualization and Analysis XLのエキサイティングな機能であるTabular Graphについてご紹介したいと思います。 IC6.1.8 ISR14/ICADVM20.1 ISR14で導入されたTabular Graph機能は、信号を表形式の列にプロットすることができます。 これまでは、選択した信号を右クリックして Send To -> Table オプションを選択すると、総合的な波形データを...
    • 8 Apr 2021
  • Breakfast Bytes: Cadence/Samsung Automotive Reference Flow

    Paul McLellan
    Paul McLellan
    Today, Cadence and Samsung announced the availability of an Automotive Reference Flow for Samsung Foundry's 14LPU process technology. In the press release back in 2016 when the process was first announced, Samsung said: Samsung’s fourth-ge...
    • 8 Apr 2021
  • Breakfast Bytes: Benedict Evans on Tech in 2021

    Paul McLellan
    Paul McLellan
    Benedict Evans used to work in Silicon Valley for Andreesen-Horowitz (a16z) but he returned to the UK (he's British). But one thing hasn't changed—he still does a big Powerpoint early in the year about the major internet trends that are driving...
    • 7 Apr 2021
  • System, PCB, & Package Design : BoardSurfers: Installation Know-How: Using Third-Party Tools with Cadence OrCAD and Allegro Products

    Shikha Jain
    Shikha Jain
    The add-on model is applicable everywhere! You can choose a basic version of the car and add-on products make it faster, nicer, or more special. Air travel add-on includes seat reservation, food, priority check-in, and extra baggage. When you purchas...
    • 6 Apr 2021
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