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Breakfast Bytes: How Do Out-of-Order Processors Work Anyway?

Paul McLellan

I've been meaning to write a post on how out-of-order processors work, but one challenge is to make the diagrams that are necessary to make it clear. Well, Jon Masters of Red Hat gave the keynote on the second day of the Linley Spring Microproces...
- 8 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Limitations of Scan Compression QoR

References4U

In this week's Whiteboard Wednesdays video, Scan Compression reduces the digital IC test time and data volume by orders of magnitude, but the technology’s limitations prevent achieving higher compression ratios. Distinguished engineer Rohit Kapur explains the different limiters of compression QoR and impact on scan design. To learn about the Cadence Modus DFT Software Solution, visit the product page at https://www.cadence…
- 7 May 2019
The India Circuit: A Special Day for Cadence India

Madhavi Rao

A few days ago, Cadence Bangalore, Noida and Pune sites had the opportunity to participate in a worldwide CSR initiative in collaboration with the NGO Rise Against Hunger (RAH). To celebrate our 30th Anniversary as a company, Cadence is partnering wi...
- 7 May 2019
Breakfast Bytes: JasperGold: the Next Generation

Paul McLellan

Formal verification has gone through a number of eras. In the early 1990s, it was an area mostly of academic interest, only able to handle toy problems. Then, in 1994, was the infamous FDIV bug. As Intel's Bob Bentley said at the 2012 Jasper User...
- 7 May 2019
Analog/Custom Design: Virtuoso Video Diary: What's New in Reliability Setup

Udit Rajput

Read this blog to know about the enhancements made to the reliability options form and to the overall reliability setup
- 7 May 2019
Breakfast Bytes: Statistical Power...or Why You Shouldn't Be Allowed to Turn Right on Red

Paul McLellan

I wrote last Friday in my post TSMC: Zero Excursion, Zero Defect about the statistical processes that are essential in semiconductor manufacturing to get high yield, and to catch any issues that arise early enough to fix them. I suspect that hig...
- 6 May 2019
Digital Design: A new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!

Priya E Joseph

“It’s not what it is, it’s about what it can become”
-The Lorax by Dr. Seuss

Have you recently reached out to open your car and received an unexpected shock…zap! There are no financial or health implications if the door handle of your car zaps you, but an Electrostatic Discharge (ESD) zap event can instantly destroy devices worth billions of dollars. Today, we are aware of the destructive…
- 5 May 2019
Breakfast Bytes: Sunday Brunch Video for 5th May 2019

Paul McLellan

https://youtu.be/ICpG3ouDIyQ Made at Nathan's Tesla (camera Sean) Monday: Andy Bechtolsheim: 85 Slides in 25 Minutes, Even the Keynote Went at 400Gbps Tuesday: Tesla Drives into Chip Design Wednesday: Linley Gwennap's Deep Dive into Deep Lear...
- 5 May 2019
System, PCB, & Package Design : BoardSurfers: Make Menus Your Own – Customizing Menus and Toolbars with Things You Use Daily

Tyler

Flexibility and the ability to customize the software/environment to your own personal needs is a definite strength of Cadence® software, and the Allegro® platform is no different. Whether you are developing your own SKILL program to make a detailed flow easier; automating a tedious, but routine, task; or just reordering commands in the menu to match your usage flow, Allegro offers you what you need. Best of all, it comes…
- 3 May 2019
PCB、IC封装：设计与仿真分析: 电路/硬件设计工程师如何选择原理图设计工具

TeamAllegro

当谈到在EDA领域选择原理图设计工具时，没有人可以找到万能的解决方案。多变的因素加之不尽相同的个人偏好，使得“最好的原理图设计工具是什么？”这个问题始终没有一个统一的答案。目前市面上的工具基本都可以完成大多数设计工作，甚至有些工具可能看起来还极其相似。在这种情况下，某一种产品能否脱颖而出则是非常主观的，简单易用、兼顾效率，成为了是否受用户欢迎的关键决定因素。通常，电路/硬件设计工程师在进行产品比较时会进行以下评估和考虑： space 使用工具之前，我需要预先学习...
- 3 May 2019
Breakfast Bytes: TSMC: Zero Excursion, Zero Defect

Paul McLellan

At the recent TSMC Technology Symposium, JK Wang, the SVP of fab operations, talked about Manufacturing Excellence. There were two parts to this: Capacity ramping and new fab status The pursuit of quality excellence Capacity Ramping and New Fab Sta...
- 3 May 2019
System, PCB, & Package Design : IC Packagers: Coming Soon to a Blog Near You…

Tyler

What is new in the Cadence® SiP Layout and APD tools? Is there reason to get excited to pick up the most recent HotFix of 17.2 (or update from release 16.6 to 17.2 at all)? The answer is a most emphatic YES. Join us as we start our jo...
- 2 May 2019
Analog/Custom Design: Virtuosity: Filtering Plots!

Arja H

If you're a regular reader of the Virtuosity series, you'll have seen a few blogs recently on filtering in Virtuoso ADE Assembler and Virtuoso ADE Explorer. Well, we've extended this capability and the same filters are now available for your plots in Virtuoso Visualization and Analysis.
- 2 May 2019
Breakfast Bytes: TSMC: Specialty Technologies

Paul McLellan

What is a "specialty technology"? Kevin Zhang, the VP of business development, told us at the recent TSMC Technology Symposium: If Yuh-Jier Mii doesn't talk about it, then it's a specialty technology Yuh-Jier Mii is the head of technology deve...
- 2 May 2019
Verification: Cadence at the Red Hat Summit--Come See Xcelium in Action!

XTeam

The Red Hat Summit is coming around to Boston this year, and it’s only a few short days away. Cadence has a demo at the Marvell booth (that’s #418-1), and we’ll be there from 3-7 PM on Wednesday, May 8^th. There, we’ll be showing off our Arm-server technology by demoing Xcelium. Be sure to stop by!

Cadence and Arm have worked together to create solutions that optimize power, performance, and area…
- 1 May 2019
Verification: Cadence at the HOST Symposium: Come See What We're Doing!

XTeam

The HOST Symposium is returning for its 12^th year, and general registration is open now. The IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) aims to accelerate and assist the development of hardware-based security technologies.

With the advent of Internet-of-Things (IoT) devices, new avenues of attack have opened up for nefarious hackers—what was previously focused on computers, defense, automotive…
- 1 May 2019
Breakfast Bytes: Linley Gwennap's Deep Dive into Deep Learning

Paul McLellan

At the recent Linley Spring Microprocessor Conference, Linley Gwennap kicked off with the opening keynote on what is clearly the biggest thing to hit processors in a long time: deep learning. Linley started with an overview of deep learning and the l...
- 1 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - SIMD Capability of B10 B20 and Some Associated Vector Processing Units

References4U

In this week's Whiteboard Wednesdays video, Pierre-Xavier Thomas shows some of the processing units of the B10/B20 supporting the SIMD architecture in the context of the operator support.

https://youtu.be/-620ZPxaYf8
- 30 Apr 2019
Analog/Custom Design: Spectre Tech Tips: Measuring Noise in Digital Circuits

RF Rich

As a designer, verification engineer, or CAD expert, you use Spectre APS for analyzing your designs. Sometimes, you use Spectre to measure noise in digital circuits. Are you confused which method to use for noise measurement since Spectre provides different methods for measuring noise? This blog discusses the different noise measuring methods and explains why they may provide different results.
- 30 Apr 2019
Analog/Custom Design: Virtuoso IC6.1.8 ISR3 and ICADVM18.1 ISR3 Now Available

Virtuoso Release Team

The IC6.1.8 ISR3 and ICADVM18.1 ISR3 production releases are now available for download.
- 30 Apr 2019
Breakfast Bytes: Tesla Drives into Chip Design

Paul McLellan

I've said for a couple of years that high-end automotive companies are going to have to do what the high-end mobile companies did, and build their own application processors. It will be the only way for them to get differentiation and built a pro...
- 30 Apr 2019
Verification: Specman Linting and the all_unique Method

teamspecman

Sorting according to pointers- why?
One of the best practices that you need to follow when using Specman or any other tool is to use a linting tool on a regular basis to catch bugs early. In Specman, we frequently add additional e checks to HAL (Cadence linting tool) based on the customer issues that can be avoided or caught during linting.

For instance, in 19.03, among few other linting checks, we planned to add a check…
- 29 Apr 2019
Breakfast Bytes: Andy Bechtolsheim: 85 Slides in 25 Minutes, Even the Keynote Went at 400Gbps

Paul McLellan

Andy Bechtolsheim likes to go fast. He famously had to rush off to a meeting but wrote Sergey and Larry $100K check to fund Google anyway, with no paperwork. At the keynote at CDNLive, he presented The Road to 400G Networking. He had 85 slides and 25...
- 29 Apr 2019
定制IC芯片设计 : Virtuosity: 在IC6.1.7 / ICADV12.3 ISR期间，我在Virtuoso可视化和分析以及ADE中遇到了什么?

Rashmi G

也许你一直被困在一个使用旧版Virtuoso 的项目上，也许你只是订阅了这些博客，或者你是Virtuoso的新用户，也许你不知道有哪些新的酷炫功能在 IC6.1.7 / ICADV12.3 ISR 的过程中添加了。我们已经添加了大量的增强功能，数量超过1600！我不能在这里详述所有这些内容，但我将概述 Virtuoso® ADE Assembler，Virtuoso® ADE Explorer 和 Virtuoso® Visualization and Analy...
- 28 Apr 2019
PCB、IC封装：设计与仿真分析: 了解AMI与IBIS之后需要知道：如何轻松完成DDR5设计

Sigrity

本文转翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章"AMI for DDR5 Made Easy"。上一篇文章介绍了IBIS和AMI，并提到了行业内正在发生的一个重大变化： DDR5标准将（间接）授权使用AMI模型。 DDR5 在预计将于今年发布的DDR5标准中，DRAM将被指定涵盖DFE（判决反馈均衡）能力。而在实践中，DFE建模就意味着创建和使用AMI模型。实际上，近十年来用于分析串行链路的技术正在扩展应用到并行存储器接口领域。然...
- 26 Apr 2019

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