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Breakfast Bytes: Cadence, McLaren, and the United States (Austin) Grand Prix

Paul McLellan

As you probably know, Cadence has a technology partnership with McLaren racing. I wrote about it when we announced it in my post Cadence Shifts into High Gear with the McLaren Formula 1 Team. If you live in the U.S., this weekend is one of the big ev...
- 21 Oct 2022
Life at Cadence: Building Confidence through the Cadence Returnship Program

Michelle Hoffmann

Re-entering the high-tech field after taking a break to prioritize family can be overwhelming. When Sanjita, Lead Application Engineer and Cadence Returnship alum, was ready to re-enter the workforce, she had to learn to navigate new technological de...
- 20 Oct 2022
System, PCB, & Package Design : Cadence OrCAD and Allegro 22.1 is Now Available

AllegroReleaseTeam

The OrCAD® and Allegro® 22.1 release is now available at Cadence Downloads. This blog post contains important links for accessing this release and introduces some of the main changes made and the new features that you can look forward to.

OrCAD/Allegro 22.1 (SPB221)

Here is a representative list of the changes and enhancements across products with brief overviews.

Allegro PCB Editor and Allegro Package Designer…
- 20 Oct 2022
Life at Cadence: IQM Is Building the Next Generation of Quantum Computers

Corporate

IQM seeks to solve one of the greatest technological challenges globally: building useful quantum computers. A spinoff of Aalto University and VTT Technical Research of Finland, IQM’s been a key player in Europe’s quantum ecosystem, havin...
- 20 Oct 2022
Life at Cadence: RISC-V Is Thriving – Here’s What You Need to Know

Corporate

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set Computer, meaning it’s designed to simplify eac...
- 20 Oct 2022
Breakfast Bytes: Latinx Heritage Month

Paul McLellan

Last week, Cadence held a Mercado Fiesta on the campus to celebrate Latinx Heritage Month. Latinx Heritage Month runs from September 15 through October 15, so it's now over. But I'm going to write about it today anyway. The celebration ...
- 20 Oct 2022
Analog/Custom Design: Start Your Engines: Clone your AMS Designer Testcases and Rerun them Anywhere

Andre Baguenie

Design Capture and Packaging (DCP) utility lets you isolate, capture and package the source files easily from your Spectre AMS Designer testbench and immediately rerun it in the same or a different environment. Check out this blog to know more.
- 20 Oct 2022
Digital Design: HLS for AI/ML Models: TensorFlow to RTL

Vinod Khera

Artificial Intelligence (AI) plays a key role in semiconductors to meet the challenging demand and rising customer expectations. But implementing these AI models in Hardware (FPGA) is challenging. AI developers generally use TensorFlow/Caffe model, w...
- 19 Oct 2022
Computational Fluid Dynamics: Augment Certainty of Bio-simulation Studies with Computational Fluid Dynamics

Veena Parthan

Computational fluid dynamic (CFD) simulations have a lot to offer for a top-level view of how the flow of different fluids can affect the drug delivery process or other bio-simulation studies for lead discovery.
- 19 Oct 2022
カスタムIC／ミックスシグナル: Spectre Tech Tips: ダイナミック電流密度チェック

Custom IC Japan

デバイスと回路の信頼性は、個々のMOSFET デバイスが短時間に消費する電力と、発生する熱の量に大きく依存しています。信頼性と寿命を向上するために、回路設計者はデザイン内のデバイスの消費電力を最適化する必要があります。Spectre 21.1 ISR10以降では、電力密度が大きいMOSFETデバイスを検出するための、新しい過渡ベースの手法がシミュレータによって提供されます。この動的なデザインチェックは dynamic power density check と呼ばれます。こ...
- 19 Oct 2022
Verification: USB4 Version 2.0 – Next frontier in High-Speed Data Tunneling

Neelabh

USB4 Version 2.0 specification was recently released by the USB Promoter Group. This specification enables up to 80 Gbps link speed per direction in symmetric mode, and up to 120 Gbps link speed in asymmetric mode. It has new feature capabilities in almost all the layers of the USB4 Version 1.0 specification, focus being on how to tunnel and transmit the data faster.

Some important feature updates in it are listed below…
- 19 Oct 2022
Computational Fluid Dynamics: Last Week at Fidelity CFD

John Chawner

It's Monday and time to look back on what happened last week here at Cadence Fidelity CFD. From the Blogs Generate Quads/Hexes at the Speed of Trias Quickly constructing a high-quality surface and volume mesh can be a tedious process, especially for ...
- 19 Oct 2022
Computational Fluid Dynamics: On-Demand Webinar - Predicting Aerodynamic Flow Around Automotive Vehicles

AnneMarie CFD

Predicting aerodynamic flow physics around automotive vehicles is a complex endeavor, leaving the engineer with the need to balance cost and accuracy. In this webinar we show the full CFD simulation workflow for car external aerodynamics, compare speed and accuracy for different turbulence modeling approaches and showcase multiple reference car models.
- 19 Oct 2022
Digital Design: Voltus Voice: How to Find Functional Power Vectors that Matter Quickly

bertrandgenneret

Vector profiling enables ASIC designers to quickly identify areas with maximum activity and power consumption when analyzing long simulation vectors, accelerating power signoff of billion-node designs. Focusing on meaningful events reduce the power signoff analysis runtime and memory usage drastically, having a direct impact on time-to-market. Check out this blog to know more.
- 19 Oct 2022
Life at Cadence: Formula 1: Hybrid Design vs. Density and Compact Design Optimization

Corporate

Understand the role that density and compact design optimization play when designing modern devices.
- 19 Oct 2022
Breakfast Bytes: USB-C – The Least Standard Standard Ever

Paul McLellan

In a post in our verification blog, Neelabh Singh told us that USB4 Version 2.0 Announced. As he said in that post: USB Promoter Group has announced the pending release of the USB4 Version 2.0 specification, which will enable up to 80Gbps operation ...
- 19 Oct 2022
Verification: Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Technique

Somya Bansal

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol that makes use of the PCIe PHY layer. It may be chosen to run the PCIe protocol in addition to one or multiple alternate protocols in the alternate protocol mode. This is negotiated by the link partners during Configuration LTSSM states while communicating their own capabilities with each other. For the CXL protocol, the same outline is utilized…
- 19 Oct 2022
Breakfast Bytes: HOT CHIPS: Arm's Morello

Paul McLellan

HOT CHIPS was back in the summer, and I covered it in two overview posts (and some others on specific topics): HOT CHIPS Day 1: Hot Chiplets HOT CHIPS Day 2: AI...and More Hot Chiplets I mentioned that I would be writing about the Arm Morello prese...
- 18 Oct 2022
System, PCB, & Package Design : Enflame Unveils Lab-Correlated Design and Analysis Methodology for 2.5D HBM Designs

Sigrity

At CadenceLIVE China 2022, AI-startup, Enflame Technology, revealed how their engineering teams have overcome silicon interposer design challenges connecting over 1700 signals between an HBM memory stack and their own priority AI-based chip design across a silicon substrate.

The discussion included HBM interface standards that range in data transfer speeds from 2.0 GHz to 7.2 GHz.

A team of Enflame Engineers supported…
- 17 Oct 2022
Verification: CXL 3.0 Scales the Future Data Center

Claire Ying

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and Gen-Z transfer specification and assets to CXL Consortium. In August, the next full version of the CXL 3.0 standard was announced. With the continued proliferation of cloud computing, AI and analytics, increasing need for system-level optimization among high performance accelerators, system memory, smart NICs and leading edge networking. The…
- 17 Oct 2022
Breakfast Bytes: CadenceLIVE Boston: State-of-the-Art Heterogeneous Integrated Packaging (SHIP)

Paul McLellan

Congress and the military love to come up with cute acronyms for programs, and so the Navy has come up with SHIP (after all, they are the Navy), which stands for State-of-the-art Heterogeneous Integrated Packaging for RF. I wrote about this topic (wi...
- 17 Oct 2022
Verification: Unraveling New Introduced PCIe 6.0 L0p

xinmu

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In ‘What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.

Amongst many new features and changes in PCIe 6.0…
- 17 Oct 2022
Computational Fluid Dynamics: Streamline Reading and Writing Files from Fidelity Pointwise

Veena Parthan

For a CFD solution, a CAD geometry goes in and a CFD mesh comes out! Only if it was as simple as it sounded. Although file management in practice is more complex than that, it need not be complicated and can be made easy using the tips and tricks for reading and writing files from Fidelity Pointwise.
- 16 Oct 2022
Verification: Unraveling PCIe 6.0 Training Sequences Update and Verification Challenges

xinmu

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.

Amongst many new features and changes in PCIe 6.0, we will…
- 14 Oct 2022
System, PCB, & Package Design : System Analysis Knowledge Bytes: Simplifying Signal and Power Integrity Analysis with Sigrity Aurora

deeptik

This System Analysis Knowledge Bytes blog describes how Sigrity Aurora can help simplify signal and power integrity analysis. It gives an overview of all the workflows available in the Allegro In-Design (IDA) Environment including the new Interconnect Model Extraction workflow.
- 14 Oct 2022

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