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Verification: USB4 Version 2.0 – Next frontier in High-Speed Data Tunneling

Neelabh

USB4 Version 2.0 specification was recently released by the USB Promoter Group. This specification enables up to 80 Gbps link speed per direction in symmetric mode, and up to 120 Gbps link speed in asymmetric mode. It has new feature capabilities in almost all the layers of the USB4 Version 1.0 specification, focus being on how to tunnel and transmit the data faster.

Some important feature updates in it are listed below…
- 19 Oct 2022
Computational Fluid Dynamics: Last Week at Fidelity CFD

John Chawner

It's Monday and time to look back on what happened last week here at Cadence Fidelity CFD. From the Blogs Generate Quads/Hexes at the Speed of Trias Quickly constructing a high-quality surface and volume mesh can be a tedious process, especially for ...
- 19 Oct 2022
Computational Fluid Dynamics: On-Demand Webinar - Predicting Aerodynamic Flow Around Automotive Vehicles

AnneMarie CFD

Predicting aerodynamic flow physics around automotive vehicles is a complex endeavor, leaving the engineer with the need to balance cost and accuracy. In this webinar we show the full CFD simulation workflow for car external aerodynamics, compare speed and accuracy for different turbulence modeling approaches and showcase multiple reference car models.
- 19 Oct 2022
Digital Design: Voltus Voice: How to Find Functional Power Vectors that Matter Quickly

bertrandgenneret

Vector profiling enables ASIC designers to quickly identify areas with maximum activity and power consumption when analyzing long simulation vectors, accelerating power signoff of billion-node designs. Focusing on meaningful events reduce the power signoff analysis runtime and memory usage drastically, having a direct impact on time-to-market. Check out this blog to know more.
- 19 Oct 2022
Life at Cadence: Formula 1: Hybrid Design vs. Density and Compact Design Optimization

Corporate

Understand the role that density and compact design optimization play when designing modern devices.
- 19 Oct 2022
Breakfast Bytes: USB-C – The Least Standard Standard Ever

Paul McLellan

In a post in our verification blog, Neelabh Singh told us that USB4 Version 2.0 Announced. As he said in that post: USB Promoter Group has announced the pending release of the USB4 Version 2.0 specification, which will enable up to 80Gbps operation ...
- 19 Oct 2022
Verification: Leveraging the PCIe for CXL Mode Link Up Using Alternate Protocol Negotiation Technique

Somya Bansal

An Alternate Protocol negotiation (APN) can be understood as a non-PCIe protocol that makes use of the PCIe PHY layer. It may be chosen to run the PCIe protocol in addition to one or multiple alternate protocols in the alternate protocol mode. This is negotiated by the link partners during Configuration LTSSM states while communicating their own capabilities with each other. For the CXL protocol, the same outline is utilized…
- 19 Oct 2022
Breakfast Bytes: HOT CHIPS: Arm's Morello

Paul McLellan

HOT CHIPS was back in the summer, and I covered it in two overview posts (and some others on specific topics): HOT CHIPS Day 1: Hot Chiplets HOT CHIPS Day 2: AI...and More Hot Chiplets I mentioned that I would be writing about the Arm Morello prese...
- 18 Oct 2022
System, PCB, & Package Design : Enflame Unveils Lab-Correlated Design and Analysis Methodology for 2.5D HBM Designs

Sigrity

At CadenceLIVE China 2022, AI-startup, Enflame Technology, revealed how their engineering teams have overcome silicon interposer design challenges connecting over 1700 signals between an HBM memory stack and their own priority AI-based chip design across a silicon substrate.

The discussion included HBM interface standards that range in data transfer speeds from 2.0 GHz to 7.2 GHz.

A team of Enflame Engineers supported…
- 17 Oct 2022
Verification: CXL 3.0 Scales the Future Data Center

Claire Ying

CXL is emerging as the industry focal point for coherent I/O with Open CAPI and Gen-Z transfer specification and assets to CXL Consortium. In August, the next full version of the CXL 3.0 standard was announced. With the continued proliferation of cloud computing, AI and analytics, increasing need for system-level optimization among high performance accelerators, system memory, smart NICs and leading edge networking. The…
- 17 Oct 2022
Breakfast Bytes: CadenceLIVE Boston: State-of-the-Art Heterogeneous Integrated Packaging (SHIP)

Paul McLellan

Congress and the military love to come up with cute acronyms for programs, and so the Navy has come up with SHIP (after all, they are the Navy), which stands for State-of-the-art Heterogeneous Integrated Packaging for RF. I wrote about this topic (wi...
- 17 Oct 2022
Verification: Unraveling New Introduced PCIe 6.0 L0p

xinmu

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In ‘What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.

Amongst many new features and changes in PCIe 6.0…
- 17 Oct 2022
Computational Fluid Dynamics: Streamline Reading and Writing Files from Fidelity Pointwise

Veena Parthan

For a CFD solution, a CAD geometry goes in and a CFD mesh comes out! Only if it was as simple as it sounded. Although file management in practice is more complex than that, it need not be complicated and can be made easy using the tips and tricks for reading and writing files from Fidelity Pointwise.
- 16 Oct 2022
Verification: Unraveling PCIe 6.0 Training Sequences Update and Verification Challenges

xinmu

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.

Amongst many new features and changes in PCIe 6.0, we will…
- 14 Oct 2022
System, PCB, & Package Design : System Analysis Knowledge Bytes: Simplifying Signal and Power Integrity Analysis with Sigrity Aurora

deeptik

This System Analysis Knowledge Bytes blog describes how Sigrity Aurora can help simplify signal and power integrity analysis. It gives an overview of all the workflows available in the Allegro In-Design (IDA) Environment including the new Interconnect Model Extraction workflow.
- 14 Oct 2022
Breakfast Bytes: Samsung Foundry Roadmap 2022

Paul McLellan

Recenty, it was the Samsung Foundry Forum (SFF). In fact, there was a pre-event for the press that morning (SFF started after lunch). I couldn't attend in person due to a personal conflict, but the press event was recorded and I received the slid...
- 14 Oct 2022
Computational Fluid Dynamics: Fidelity Pointwise 2022.1 Hot Fix 2 Now Available

AnneMarie CFD

Fidelity Pointwise 2022.1 Hot Fix 2 is now available for download and production use. Discover it's new features and download instructions.
- 14 Oct 2022
Academic Network: Shift-Left Methodology for the Development of Hardware Accelerators Education Kit Is Available Now

Anton Klotz

In order to describe the purpose of this education kit, let’s leave the EDA turf for a minute and enter the world of computer architecture. If you still remember the 80s, the PCs of that time had one single CPU (Central Processing Unit), which ...
- 13 Oct 2022
Life at Cadence: Hassle-Free Rigid-Flex PCB Bending EM Analysis

Ben Gu

The functionality, safety, and effectiveness of devices using rigid-flex PCBs are highly critical, especially for devices used in advanced medical implants, high-precision critical military equipment, and similar regulated and classified devices, mak...
- 13 Oct 2022
Life at Cadence: Butterfly Network Puts Ultrasound on a Chip with Cadence

Corporate

About two-thirds of the world’s population lacks access to medical imaging, whether in developing nations or in first-world countries with underserved communities. Butterfly Network, however, has a solution, and it’s built on a single chi...
- 13 Oct 2022
Breakfast Bytes: 2022 Kaufman Award Honors Giovanni De Micheli

Paul McLellan

This year's Kaufman Award honors Giovanni De Micheli, usually known as Nanni. Of course, with a name like that, you will guess correctly that he is Italian. However, despite being brought up in Italy, his career has spanned two main parts, neither of...
- 13 Oct 2022
Verification: Unraveling PCIe 6.0 FLIT Mode Challenges

xinmu

The PCIe 6.0 Specification released in 2021 doubles the performance to 64GT/s transfer rate with PAM4 (Pulse Amplitude Modulation with 4 levels) modulation and uses FLIT (Flow Control Unit) as the unit of communication for efficiency. In ‘What Disruptive Changes to Expect from PCI Express Gen 6.0? we covered what significant features PCIe 6.0 evolved to embrace.

Amongst many new features and changes in PCIe 6.0…
- 12 Oct 2022
Analog/Custom Design: Virtuoso ICADVM20.1 ISR28 and IC6.1.8 ISR28 Now Available

Virtuoso Release Team

The ICADVM20.1 ISR28 and IC6.1.8 ISR28 production releases are now available for download.
- 12 Oct 2022
Verification: Importance of MDIO Interface for Ethernet.

AyushK

Media Independent Interface Management (MIIM), or Management Data Input/Output (MDIO), is a serial bus protocol and is used for the IEEE 802.3 Ethernet standard and Media Independent Interface (MII). The MIIM/MDIO protocol is a simple two-wire serial interface with specific terminology to define the various devices on the bus. The device driving the MDIO bus is identified as the Station Management Entity (STA). The STA…
- 12 Oct 2022
Life at Cadence: How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?

Vinod Khera

The chip design industry is going through exciting times. Process nodes with smaller geometries have always enticed chip manufacturers and OEMs, as it helps integrate more functionality over SoC. This reduction in the process nodes has been predicted...
- 12 Oct 2022

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