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Latest Blog Posts

  • Breakfast Bytes: Cadence Expands into Molecular Simulation with Acquisition of OpenEye Scientific

    Paul McLellan
    Paul McLellan
    This morning, Cadence announced that it has entered into a definitive agreement to acquire privately held OpenEye Scientific Software Inc, a leading provider of computational molecular modeling and simulation software being increasingly used by ...
    • 25 Jul 2022
  • Analog/Custom Design: Spectre Tech Tips: Introducing Spectre X EMIR Voltus-XFi

    Stefan Wuensche
    Stefan Wuensche
    This blog describes the new capabilities in Spectre 21.1 ISR2 through which it provides support to the Voltus-XFi Custom Power Integrity Solution.
    • 22 Jul 2022
  • Breakfast Bytes: CadenceLIVE: Pegasus on AWS, Let Physical Verification Fly

    Paul McLellan
    Paul McLellan
    At CadenceLIVE Silicon Valley, Ahmed Elzeftawi of AWS and Dibyendu Goswami of Cadence presented Pegasus TrueCloud for Gigascale Physical Verification using Hybrid Cloud on AWS. Amed is a Senior Partner Solutions Architect for Semiconductors and EDA, ...
    • 22 Jul 2022
  • Cadence Academic Network at 59DAC

    Academic Network: Cadence Academic Network at 59DAC

    Kira Jones
    Kira Jones
    The Cadence Academic Network was excited to participate in many activities at the 2022 Design Automation Conference (DAC) held at the Moscone Center in San Francisco from July 10-14. We were proud to sponsor the DAC Young Fellows Program and Ph.D. Fo...
    • 21 Jul 2022
  • System, PCB, & Package Design : In-Design Analysis in the Cloud with Cadence OnCloud

    Sherry Hess
    Sherry Hess
    Last month at CadenceLive Silicon Valley, Cadence introduced a software-as-a-service (SaaS) cloud platform - aka OnCloud.  This new offering provides designers with instant access to system design and analysis products, namely in-design mul...
    • 21 Jul 2022
  • Breakfast Bytes: ITF USA: Luc Van den hove on Deep Tech

    Paul McLellan
    Paul McLellan
    The afternoon of the Monday of SEMICON West is always the Imec Technology Forum (ITF) USA, held in the Marriott. Now that DAC is co-located with SEMICON West, this doesn't work so well since there are presentations at both events that overlap. Howeve...
    • 21 Jul 2022
  • System, PCB, & Package Design : System Analysis Knowledge Bytes: Accelerating Early Stage Design Sign-Off Using PCIe 5.0 Compliance Kit in Topology Workbench

    Akshaya Kumar
    Akshaya Kumar
    This blog talks about how the Cadence®︎ AdvancedSI tools, which are packaged in the Topology Workbench environment, support the complete PCIe 5.0 channel characterization.
    • 20 Jul 2022
  • Breakfast Bytes: CadenceLIVE: Do You Know What CMP Is?

    Paul McLellan
    Paul McLellan
    I was talking to someone at Cadence recently and I was surprised that he didn't know what CMP is. To me, it is one of the most unlikely steps in the manufacture of integrated circuits. CMP stands for chemical-mechanical-polishing or chemical-mech...
    • 20 Jul 2022
  • System, PCB, & Package Design : Shift Left: Moving Multiphysics into the Mainstream

    Sherry Hess
    Sherry Hess
    As electronic systems have grown incrementally more complex, with more features packed into a smaller footprint, signal rates rising, and production schedules becoming ever more aggressive, there simply is no room or time for multiple design cycles and prototype failures. To succeed in today’s highly competitive electronics markets, a practice called “shift left” is becoming increasingly popular.
    • 19 Jul 2022
  • Breakfast Bytes: Andreas Kuehlmann and Tortuga Logic...I Mean Cycuity

    Paul McLellan
    Paul McLellan
    I was in San Francisco for the RSA security conference. On Monday, it has tutorials and the conference has its opening keynote at 3 pm. So I had lunch with Andreas Kuehlmann. At the time of our lunch, he was CEO of Tortuga Logic, but the company has ...
    • 19 Jul 2022
  • RF /マイクロ波設計: μWaveRiders:新しいPythonライブラリは、Cadence AWR Design Environmentで高レベルのAPIを提供します

    RF Design Japan
    RF Design Japan
    新しいPythonライブラリは、Pythonのコーディング規則により厳密に準拠したコマンド構造を使用して、PythonとAWRソフトウェア間のインターフェイスを容易にするために作成されました。 このライブラリには「pyawr-utils」というラベルが付いており、標準のPythonpipコマンドを使用してインストールされます。 pyawr-utilsをインストールして使用するための包括的なドキュメントが利用可能です。
    • 18 Jul 2022
  • RF Engineering: μWaveRiders: New Python Library Provides a Higher-Level API in the Cadence AWR Design Environment

    TeamAWR
    TeamAWR
    A new Python library has been written to facilitate an interface between Python and AWR software using a command structure that adheres more closely to Python coding conventions. This library is labeled "pyawr-utils" and it is installed using the standard Python pip command. Comprehensive documentation for installing and using pyawr-utils is available.
    • 18 Jul 2022
  • Breakfast Bytes: June Update: CHIPS, Minis, and DI Water

    Paul McLellan
    Paul McLellan
    My monthly update normally occurs on the last Friday of the month. But for June, that was two weeks ago. Cadence was off for an extended July 4th break, and then I was on vacation, and then DAC, so I decided to make today the honorary last Friday of ...
    • 18 Jul 2022
  • Xcelium PowerPlayBack App and Dynamic Power Analysis

    Verification: Xcelium PowerPlayBack App and Dynamic Power Analysis

    Vinod Khera
    Vinod Khera
    Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay of waveforms for glitch-accurate power estimation of multi-billion gate SoC designs.
    • 18 Jul 2022
  • Breakfast Bytes: Sunday Brunch Video for 17th July 2022

    Paul McLellan
    Paul McLellan
    https://youtu.be/ogP4BoGLEW4 Made with Lumen5 Monday: Cadence Acquires Future Facilities, a Pioneer in Datacenter Digital Twins Tuesday: DAC 2022: Day 1 Wednesday: DAC 2022: Day 2 Thursday: DAC 2022: Day 3 Friday: Cadence and MathWorks Announce Flow ...
    • 17 Jul 2022
  • System, PCB, & Package Design : Ascent: Training Insights: Managing Design Variations in Allegro System Capture

    Supriya Srivastava
    Supriya Srivastava
    Assembling the board is one of the last yet crucial steps in the PCB development process. A careful selection of components is of paramount importance especially before you send out the final components for assembly. Even a small modification in a co...
    • 15 Jul 2022
  • Breakfast Bytes: Cadence and MathWorks Announce Flow from MATLAB to RTL

    Paul McLellan
    Paul McLellan
    Today in Yokohama at CadenceLIVE Japan, Cadence announced a new MATLAB/Stratus flow integration jointly developed and supported by MathWorks and Cadence. This automates the path from MATLAB to Stratus and RTL allows an automatic flow from MATLAB thro...
    • 15 Jul 2022
  • System, PCB, & Package Design : System Analysis Knowledge Bytes: Cadence Celsius Thermal Solver: A Complete Thermal Solution with FEA and CFD

    Sivaprakasam S
    Sivaprakasam S
    This blog introduces Cadence Celsius Thermal Solver, the industry’s first complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures.
    • 14 Jul 2022
  • カスタムIC/ミックスシグナル: Spectre Tech Tips: 精度101

    Custom IC Japan
    Custom IC Japan
    Spectreを含むアナログ回路シミュレータは、求める測定値に応じてシミュレータのパラメータをパッケージとして切り替え、最適な精度と性能のバランスを得るための精度モードが用意されています。Spectre APSにはconservative、moderate、liberalの3つのerrpresetモードがあります。Spectre XにはCX、AX、MX、LX、VXの5つのpresetモードがあります。結果の精度に影響を与える主なシミュレータのパラメータを理解することが重要です。 アナログシミュレ...
    • 14 Jul 2022
  • Breakfast Bytes: DAC 2022: Day 3

    Paul McLellan
    Paul McLellan
    On to day 3 and the final day that I will be posting about. My posts on the first two days are: DAC 2022: Day 1 DAC 2022: Day 2 Machine Learning for Real: Why Principles, Efficiency, and Ubiquity Matter The keynote on Wednesday was by Steve Teig, C...
    • 14 Jul 2022
  • New Tricks from the Old Towing Tank

    Computational Fluid Dynamics: New Tricks from the Old Towing Tank

    Veena Parthan
    Veena Parthan
    Towing a ship model into a humongous basin of water allows naval architects to identify and understand the different factors that contribute to the seakeeping, maneuvering, and icebreaking capabilities of the ship.
    • 13 Jul 2022
  • Breakfast Bytes: DAC 2022: Day 2

    Paul McLellan
    Paul McLellan
    I covered Day 1 (and Day 0) of the Design Automation Conference in my post yesterday DAC 2022: Day 1. Tuesday was Day 2. The keynote sessions started off with awards. Anirudh Devgan, Cadence's CEO, is the honoree of the 2021 Kaufman Award. He rec...
    • 13 Jul 2022
  • Jasper C2RTL App for Datapath Verification

    Verification: Jasper C2RTL App for Datapath Verification

    Vinod Khera
    Vinod Khera
    Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every circumstance is difficult to achieve with conventional verification. Learn more how Jasper C2RTL App helps to perform equivalence checking with 100x performance improvement
    • 12 Jul 2022
  • GPPS 2nd Turbomachinery CFD Workshop Evaluates RANS Solvers

    Computational Fluid Dynamics: GPPS 2nd Turbomachinery CFD Workshop Evaluates RANS Solvers

    AnneMarie CFD
    AnneMarie CFD
    The GPPS 2nd Turbomachinery CFD workshop, co-organized by Cadence, will take place as part of the GPPS Chania22 conference, on September 11, 2022. This workshop aims to evaluate and improve users’ trust in RANS turbomachinery solvers by conducting a validation and verification (V&V) study on two cases: the TUDA-GLR-OpenStage transonic axial compressor and the BUAA low speed large scale axial compressor-Stage B.
    • 12 Jul 2022
  • Breakfast Bytes: DAC 2022: Day 1

    Paul McLellan
    Paul McLellan
    It's the Design Automation Conference and it is taking place in person in San Francisco. Last year's conference ended up being in-person in San Francisco last December, but it was a very muted affair with some companies not showing up at all, and oth...
    • 12 Jul 2022
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