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The India Circuit: Playing for Good

Madhavi Rao

Last Saturday, Cadence and Concern India Foundation hosted a very special event - a charity sports tournament for corporates called “5Cs” – the Corporate Citizenship Challenge for the Cause of Children. It is one of the most fun eve...
- 18 Feb 2020
Breakfast Bytes: DVCon 2020 Preview

Paul McLellan

Coming up to the big conferences like DAC, I like to do one or more preview posts, both as a service for people who are already going to help them decide what to attend, and also to encourage people in the industry to attend. DVCon is another confere...
- 18 Feb 2020
Breakfast Bytes: Sunday Brunch Video for 16th February 2020

Paul McLellan

https://youtu.be/uc_vrZsq-2I Made in Cadence parking lot (camera Steve Brown) Monday: Benedict Evans 2020: Standing on the Shoulders of Giants Tuesday: Benedict Evans 2020: Regulating the Giants Wednesday: System Analysis: Computational Software...
- 16 Feb 2020
System, PCB, & Package Design : BoardSurfers: PCB Electronics—Why Use Via Arrays?

mrigashira

We all know the ubiquitous via. What is it after all but a way to make electrical connections in a multi-layered PCB? But if you think about it, it must have been a clever ....
- 14 Feb 2020
Breakfast Bytes: Quines on Valentine's

Paul McLellan

Monday is President's Day and Cadence is off so, as has become traditional, I write about something off-topic the day before. Today's topic is self-reproducing programs. A self-reproducing program is also known as a Quine. The term Quine was ...
- 14 Feb 2020
Analog/Custom Design: Virtuosity: Updated Virtuoso ADE Explorer and ADE Assembler RAKs in IC6.1.8/ICADVM18.1 ISR9

Arja H

To show the latest features in IC6.1.8/ICADVM18.1 ISR9, we've updated the Rapid Adoption Kits for Virtuoso ADE Assembler and Virtuoso ADE Explorer. In addition, we have updated the RAK that explains the Stimuli Assignment form.
- 13 Feb 2020
Breakfast Bytes: Under the Hood of Clarity and Celsius Solvers

Paul McLellan

Yesterday, in my post System Analysis: Computational Software at Scale, I talked about computational software at scale and the three aspects that Cadence is delivering: Algorithms that operate on unimaginably huge amounts of data Scaling algori...
- 13 Feb 2020
Breakfast Bytes: System Analysis: Computational Software at Scale

Paul McLellan

In about 2000, when I was the VP of Strategic Marketing for Cadence, I got a strange voicemail that started "This is Regis McKenna...". If you are old enough, you know that Regis, and his PR firm Regis McKenna Inc, was a legend in&nbsp...
- 12 Feb 2020
Academic Network: Third Annual RESCUE Winter Workshop

Marianne Paz

Cadence hosted the third annual RESCUE Winter Workshop from 14th to 22nd of November 2019, in Feldkirchen, Germany. The Winter Workshop is an annual event attended by the RESCUE participants. Cad...
- 11 Feb 2020
System, PCB, & Package Design : IC Packagers: RF Symbols, Coils, and Structures in IC Packages

Tyler

So, you need to add more complicated structures into your package design. What options do you have available to you in the Cadence packaging products with the 17.4 release – whether you’re using the base Allegro Package Designer Plus or h...
- 11 Feb 2020
Breakfast Bytes: Benedict Evans 2020: Regulating the Giants

Paul McLellan

This is the second post about Benedict Evans' annual big presentation about the internet. Part 1 appeared yesterday in my post Benedict Evans 2020: Standing on the Shoulders of Giants. Regulation We connected everyone... including the bad people....
- 11 Feb 2020
Verification: Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple

Neelabh

Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality.

The diagram below shows two lane adapters connected to each other and each going through the link training process. Each training sub-state transition is contingent on conditions for both transmission and reception of relevant ordered sets needed…
- 10 Feb 2020
Digital Design: Library Characterization Tidbits: Liberate MX for Memory Characterization Video Series

Jommy

As we embark upon our blogging journey again in 2020, in this Library Characterization Tidbits series, we want to draw your attention to an informative video series on memory characterization, which is available on the Cadence support portal.
- 10 Feb 2020
Breakfast Bytes: Benedict Evans 2020: Standing on the Shoulders of Giants

Paul McLellan

For the last five or six years, Benedict Evans worked at Andreesen-Horowitz (a16z) and would do a big presentation on the state and future of the internet at the end of each year. He recently left a16z to return to the UK (he's English) and so hi...
- 10 Feb 2020
Breakfast Bytes: Sunday Brunch Video for 9th February 2020

Paul McLellan

https://youtu.be/CVbxaO8cVoM Made in Steve's office (camera Steve Brown) Monday: Persistent Memory at Twitter Tuesday: How Technologies Get into EDA Wednesday: The Signal Integrity Story Thursday: Exadata: An Epic Journey at Oracle with Persisten...
- 9 Feb 2020
Academic Network: Certified TowerJazz-Cadence Analog Lab at KPI in Ukraine

Anton Klotz

Around one year ago TowerJazz VP, Ori Galzur, contacted us and suggested to start a collaboration with academia in Ukraine. TowerJazz is an Israeli-US foundry for analog circuits, mainly image sensors, automotive, silicon photonics and RF, with over ...
- 7 Feb 2020
Analog/Custom Design: Virtuosity: Blogging Journey of Virtuoso Place and Route in 2019

Parula

To support various new features and enhancements in Virtuoso Placement and Routing, our tech gurus and the writers collaborated to publish some informative blogs in 2019. This blog is a sneak peek into the blogging journey of Virtuoso Placement and Routing and provides you a handy summary to make it easy for you to read these blogs at your leisure.
- 7 Feb 2020
Breakfast Bytes: How Is the C Compiler Written in C?

Paul McLellan

Often compilers for computer programming languages are written in their own language. This is less true now that so many compilers are based on complete compiler production systems such as LLVM. LLVM is written in C and C++ but has compilers for a hu...
- 7 Feb 2020
Computational Fluid Dynamics: Boom Supersonic: Relaunching Commercial Supersonic Aircraft Travel

AnneMarie CFD

Authors: Michael Rybalko, Aeropropulsion Engineer, Boom Supersonic & Jean-Charles Bonaccorsi, Technical Director, NUMECA USA Founded in 2014 in Denver, Colorado, Boom Supersonic is redefining what it means to fly by building Overture, history&r...
- 6 Feb 2020
Breakfast Bytes: Exadata: An Epic Journey at Oracle with Persistent Memory

Paul McLellan

A couple of weeks ago was the Persistent Memory Summit 2020. See my post Persistent Memory: We Have Cleared the Tower for an overview. This week I am covering two presentations, from Twitter and Oracle. There were a number of othe...
- 6 Feb 2020
Verification: A Specman/e Syntax for Sublime Text 3

teamspecman
We're happy to have guest blogger Thorsten Dworzak, Principal Consultant at Verilab GmbH, describe how he added Specman/e syntax to Sublime Text 3:
According to the 2018 StackOverflow Developer Survey, the popularity of development environments (IDEs, Text Editors) among software developers shows the following ranking:

Visual Studio Code 34.9%

Visual Studio 34.3%

Notepad++ 34.2%

Sublime Text 28.9%

Vim 25.8%

IntelliJ…
- 5 Feb 2020
Breakfast Bytes: The Signal Integrity Story

Paul McLellan

Yesterday, I started to talk about how new technologies find their way over time into EDA tools in my post How Technologies Get into EDA. Let's look at signal integrity as an example. We used not to worry about signal integrity at...
- 5 Feb 2020
System, PCB, & Package Design : IC Packagers: A Boundless Bounty of Bounding Shapes

Tyler

How’s that for a tongue twister? Go ahead, try and say it three times fast! What we’re talking about today is the “Create Bounding Shapes” tool found in the Shapes menu of both Allegro Package Designer and SiP Layout. We first...
- 4 Feb 2020
System, PCB, & Package Design : BoardSurfers: High-Speed Design Signal Integrity Challenges and Solutions

mrigashira

Usually, people start a blog by stating something dramatic and we used to bring drama to our otherwise staid stuff on PCB design by mentioning High Speed and Signal Integrity. No more. High-speed is the norm because even if your data is not in the ra...
- 4 Feb 2020
Breakfast Bytes: How Technologies Get into EDA

Paul McLellan

When I was last at Cadence around 2000, I ran what was then Custom IC. It was a different grouping from what we call CPG today, I had physical verification (remember Dracula? Vampire? Assura? Diva?) but not PCB. Of course Virtuoso and Spect...
- 4 Feb 2020

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