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Latest Blog Posts

  • Verification: A Specman/e Syntax for Sublime Text 3

    teamspecman
    teamspecman
    We're happy to have guest blogger Thorsten Dworzak, Principal Consultant at Verilab GmbH, describe how he added Specman/e syntax to Sublime Text 3:

     According to the 2018 StackOverflow Developer Survey, the popularity of development environments (IDEs, Text Editors) among software developers shows the following ranking:

    1. Visual Studio Code 34.9%
    2. Visual Studio 34.3%
    3. Notepad++ 34.2%
    4. Sublime Text 28.9%
    5. Vim 25.8%
    6. IntelliJ…
    • 5 Feb 2020
  • Breakfast Bytes: The Signal Integrity Story

    Paul McLellan
    Paul McLellan
    Yesterday, I started to talk about how new technologies find their way over time into EDA tools in my post How Technologies Get into EDA. Let's look at signal integrity as an example. We used not to worry about signal integrity at...
    • 5 Feb 2020
  • System, PCB, & Package Design : IC Packagers: A Boundless Bounty of Bounding Shapes

    Tyler
    Tyler
    How’s that for a tongue twister? Go ahead, try and say it three times fast! What we’re talking about today is the “Create Bounding Shapes” tool found in the Shapes menu of both Allegro Package Designer and SiP Layout. We first...
    • 4 Feb 2020
  • System, PCB, & Package Design : BoardSurfers: High-Speed Design Signal Integrity Challenges and Solutions

    mrigashira
    mrigashira
    Usually, people start a blog by stating something dramatic and we used to bring drama to our otherwise staid stuff on PCB design by mentioning High Speed and Signal Integrity. No more. High-speed is the norm because even if your data is not in the ra...
    • 4 Feb 2020
  • Breakfast Bytes: How Technologies Get into EDA

    Paul McLellan
    Paul McLellan
    When I was last at Cadence around 2000, I ran what was then Custom IC. It was a different grouping from what we call CPG today, I had physical verification (remember Dracula? Vampire? Assura? Diva?) but not PCB. Of course Virtuoso and Spect...
    • 4 Feb 2020
  • Breakfast Bytes: Persistent Memory at Twitter

    Paul McLellan
    Paul McLellan
    A couple of weeks ago was the Persistent Memory Summit 2020. See my post Persistent Memory: We Have Cleared the Tower for an overview. This week I am going to cover two presentations, one from Twitter and one from Oracle. There were a number of ...
    • 3 Feb 2020
  • Verification: USB3, PCIe, DisplayPort Protocol Traffic Finding its Way Through USB4 Routers

    Neelabh
    Neelabh

    USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each ingress adapter. An entry of a routing table maps an incoming HopID, called Input/Ingress HopID to a corresponding pair of Output/Egress Adapter and Egress/Output HopID.

    The responsibility of programming routing tables lies with…

    • 1 Feb 2020
  • Breakfast Bytes: Persistent Memory: We Have Cleared the Tower

    Paul McLellan
    Paul McLellan
    Last week it was the Persistent Memory Summit 2020, which has been running annually since 2013. Jim Pappas gave the state of the union address to open the summit. Back in 2017, he used a space analogy where you just need to mix hydrazine and nitrogen...
    • 31 Jan 2020
  • Breakfast Bytes: Quarry Bank Mill: A Technology Museum from the Industrial Revolution

    Paul McLellan
    Paul McLellan
    A couple of years ago (and from time to time since) I wrote a series of blog posts about technology museums. Here are the links: The Intel Museum German Computer Museums British Computer Museums The Computer History Museum Four Early Computers 1&amp...
    • 30 Jan 2020
  • Breakfast Bytes: Sigrity Aurora: In-Design Analysis

    Paul McLellan
    Paul McLellan
    Cadence's new Sigrity Aurora puts all the power of the Sigrity engines under the Allegro user experience. The new capability allows a team to go from preliminary exploration, through design, to final verification and signoff, all in the context o...
    • 29 Jan 2020
  • Intelligent System Design

    Life at Cadence: Intelligent System Design

    Corporate
    Corporate
    Electronics technology is proliferating to new, creative applications and appearing in our everyday lives. To compete, system companies are increasingly designing their own semiconductor chips and semiconductor companies are delivering software stac...
    • 28 Jan 2020
  • System, PCB, & Package Design : IC Packagers: Mysteries Revealed - Why Is Flip-Chip Chip-Down the Default Library Die Orientation?

    Tyler
    Tyler
    We’ve come to the end of my New Year’s Resolutions for 2020. Before we dive deeper into the exciting new capabilities to be found in the 17.4 release, though, I’d like to address a question I hear from new users all the time. That q...
    • 28 Jan 2020
  • Breakfast Bytes: IEDM: Novel Interconnect Techniques Beyond 3nm

    Paul McLellan
    Paul McLellan
    During the short course on the Sunday before IEDM, Chris Wilson of imec presented Novel Interconnect Techniques for Advanced Devices Beyond 3nm. In some ways, this is a complementary presentation to the one given by TSMC that I covered last week in I...
    • 28 Jan 2020
  • Breakfast Bytes: RIP Clayton Christensen

    Paul McLellan
    Paul McLellan
    Clayton Christensen died last Thursday, at the relatively young age of 67. He was the author of what I think is the best book on strategy for high-tech organizations, The Innovator's Dilemma. I have purchased several copies since I first read it,...
    • 27 Jan 2020
  • Analog/Custom Design: Virtuosity: Reminiscing About The Last 'Teen' Year of Custom IC Design Blogs

    Dishika Majumdar
    Dishika Majumdar
    If you have missed reading any of our Virtuosity, Virtuoso Meets Maxwell, Virtuoso Video Diary blogs that were published in 2019, or you would like to go back to an ISR release announcement to see what were the featured enhancements, here's your chance to bookmark this blog for all that interesting information and for some of our most-viewed posts from the last year. Also, stay tuned to our new content arriving soon.
    • 24 Jan 2020
  • Breakfast Bytes: IEDM: TSMC on 3nm Device Options

    Paul McLellan
    Paul McLellan
    At IEDM in December, Jin Cai of TSMC presented Device Technology for 3nm Node and Beyond during the short course on Sunday. He divided his presentation up into four parts: Historical CMOS scaling trends FinFET improvements Nanosheet advantages ...
    • 24 Jan 2020
  • System, PCB, & Package Design : BoardSurfers: Leveraging IPC-2581 Spec Element Capabilities to Streamline Design and Manufacturing Relationship

    Monika
    Monika
    If you are a PCB designer and follow IPC-2581 guidelines to design a board, this soluti....
    • 23 Jan 2020
  • Breakfast Bytes: DesignCon 2020: SI, PCB, Packaging, Photonics

    Paul McLellan
    Paul McLellan
    Next Tuesday through Thursday, January 28 to 30, DesignCon 2020 takes place in the Santa Clara Convention Center. it is actually their 25th anniversary. I think of DesignCon as being about everything other than chip design, but increasingly the focus...
    • 23 Jan 2020
  • System, PCB, & Package Design : DATA Pulse: Simplify Your ECAD Data Release Process While Ensuring Process Control

    Auromala
    Auromala
    Do you dread your ECAD to PLM publishing process? If yes, worry not. We have a solution.
    • 22 Jan 2020
  • Breakfast Bytes: IEDM: Automating DTCO for 3nm

    Paul McLellan
    Paul McLellan
    At IEDM in December, Lars Liebmann of TEL presented Design Technology Co-Optimization for 3nm and Beyond. The challenge in designing a modern process is that scaling is no longer based on incremental change purely at the process level. Design Te...
    • 22 Jan 2020
  • 定制IC芯片设计 : Virtuosity:Modgen中的布局重用流程

    Aneesh Shastry
    Aneesh Shastry
    Modgen 现在支持布局重用流. 请继续阅读,了解如何使用此功能通过减少创建 Modgen 的时间和精力来提高版图效率.
    • 21 Jan 2020
  • System, PCB, & Package Design : IC Packagers: Symbol Editing in IC Packages - Choose the Right Option

    Tyler
    Tyler
    When you need to make an edit to a component, whether that is the BGA footprint in need of a pin #1 padstack change for reference of adjustments to the entire bump layout of a flip-chip to feed routability changes back to the IC design team, there ar...
    • 21 Jan 2020
  • Breakfast Bytes: A Big Problem with Big Data

    Paul McLellan
    Paul McLellan
    I happened to read a blog post that referred to a 2018 paper in The Annals of Applied Statistics with the title Statistical Paradises and Paradoxes in Big Data: Law of Large Populations, Big Data Paradox, and the 2016 Presidential Election. The ...
    • 21 Jan 2020
  • 定制IC芯片设计 : 技术性:器件的自动布局和布线 — 基于行的器件放置

    Sravasti
    Sravasti
    Device-level automatic placer允许您以约束和网格兼容的方式放置器件和设备组. 您可以使用交互式设备放置选项半自动放置设备.
    • 21 Jan 2020
  • Breakfast Bytes: Sunday Brunch Video for 19th January 2020

    Paul McLellan
    Paul McLellan
    https://youtu.be/O90mUZyWIeE Made at Lick Observatory (camera Carey Guo) Monday: Details of TSMC's IEDM Presentation on N5 Tuesday: Mark Cuban on Media and AI Wednesday: 5G in 2020 Thursday: Emerging Memory Friday: Off-topic: Picas...
    • 19 Jan 2020
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