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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Dealing with AOCVs in SRAMs

Systems on Chip, or SoCs as they’re more commonly called, have become increasingly…

• 4 min read
legato , custom/analog , Monte Carlo analysis , Monte Carlo , Spectre , Custom IC Design , Custom IC

Breakfast Bytes

Foundry Roadmaps: Intel, Samsung

I definitely had cognitive dissonance at the ARM foundry talks at TechCon. The first…

• 6 min read
Intel , ARM Techcon , Samsung , TSMC , icf , FinFET , 7nm , ARM , EUV , Techcon , FD-SOI

Verification

Slaying the Gate-Level Simulation (GLS) Dragon: Your Knight Is Here!

Even today, gate-level simulation is still a major signoff step for most semiconductor…

• 2 min read
app note , Functional Verification , GLS

Breakfast Bytes

What's For Breakfast? Video Preview November 20th to 22nd 2017

https://youtu.be/aLx0C8H6qt8 Coming from Second Harvest Food Bank, San Jose (camera…

• less than a min read
thanksgiving , alto , xerox , PARC

Breakfast Bytes

IEDM Preview 2017

Every December is IEDM, the IEEE International Electron Devices Meeting (IEDM). This…

• 5 min read
Intel , IBM , 3D NAND , copper , FinFET , GlobalFoundries , MRAM , IEDM , electron devices

Whiteboard Wednesdays

Whiteboard Wednesdays - Simplifying Fault Injection Simulations for Functional Safety…

In this week's Whiteboard Wednesday, YJ Patil answers the "What", "Why", and "How…

• less than a min read
Automotive , Whiteboard Wednesdays , functional safety

Breakfast Bytes

Jasper User Group 2017

This year's Jasper User Group (JUG) took place on 7th November. It was the 10th JUG…

• 6 min read
Jasper User Group , aruba , JUG , formal , ARM , JasperGold

Breakfast Bytes

How's Technology in Israel?

Last week was the last CDNLive of 2017 (cats have nine lives, Cadence had nine CDNlives…

• 10 min read
CDNLive , mellanox , machine learning , Lip-Bu Tan , Anirudh Devgan , eyal wladman , Israel

Learning and Support

Using Search Filters to Improve Search Results on support.cadence.com

While using any search engine, you might often feel there is too much information…

• 1 min read
COS , Search Filters , Search , Cadence Online Support , Cadence Support Portal , Cadence support

Analog/Custom Design

Virtuosity: All New XStream In - The Translation Expressway

A layout design has to go through several iterations and multiple data exchanges…

• 6 min read
xstream in , design data translator , xstream in import , eda import

Breakfast Bytes

Arm Security Manifesto...and Krack

The Internet of Things (IoT) could be a big number...20 billion things... 50 billion…

• 7 min read
security , ARM Techcon , Simon Segars , security manifesto , reaper , wi-fi , mira , ARM , krack

Digital Design

How to Measure and Improve Design Regularity for Better Yield

The following post is an excerpt of “Methodology for Analyzing and Quantifying Design…

• 1 min read
pattern analysis , machine learning , analytics , yield , silicon signoff , design for manufacturing , DFM

Breakfast Bytes

Social Engineering

The biggest weakness in security are the people. It is almost never the encryption…

• 6 min read
security , spearphishing , phishing , social engineering , ARM , ddos , Techcon

System, PCB, & Package Design 

How to Be Sure Your PCB Design Is Protected from ESD Events

One way to determine if your design can withstand an electro-static discharge (ESD…

• 4 min read
Time domain , Speed2000 , FDTD , Sigrity , ESD

Verification

Adding Annotations in Your e Code

If you have had a chance to work with languages like Java or C#, you might have come…

• 6 min read
Specman , e , e language , specman elite , annotations

The India Circuit

The Exciting New Product Launched at CDNLive India 2017

One of the highlights at CDNLive India 2017 that was held in September was the launch…

• 3 min read
memory characterization , CDNLive India , cadence , Vinod Kariat , Cadence Legato , Invecas

Breakfast Bytes

Simon Segars: It's the Security, Stupid

Simon Segars opened the second day of Arm TechCon (or for exhibitors who didn't notice…

• 9 min read
security , ARM Techcon , Simon Segars , softbank , ARM , krack

Breakfast Bytes

What's For Breakfast? Video Preview November 13th to 17th 2017

https://youtu.be/Ar6PcH48DNo Coming from David Intercontinental Tel Aviv (camera…

• less than a min read
ARM Techcon , artificial intelligence , Jasper User Group , deep learning , CDNLive , JUG , Samsung , TSMC , intel custom foundry , caspa , cdnlive israel , ARM , IEDM

Whiteboard Wednesdays

Whiteboard Wednesdays - A Practical Approach to Failure Modes, Effects, and Diagnostic…

In this week's Whiteboard Wednesday, John MacLaren explains the steps required for…

• less than a min read
Automotive , Whiteboard Wednesdays , DDR4 , DDR , DDR3
CDNS - Fix Layout Hompage