Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

"Alexa, What Is HiFi 5?"

"Alexa, turn on the living room light." "Okay." "Alexa, what is Cadence announcing…

• 4 min read
hifi 5 , alexa , audio , voice recogntion , Tensilica

Whiteboard Wednesdays

Whiteboard Wednesdays – Machines with Voice UI and Tensilica HiFi 5 DSP

In this week’s Whiteboard Wednesdays video, Sachin Ghanekar talks about the new Tensilica…

• less than a min read
Whiteboard Wednesdays , HiFi DSP , neural networks

Analog/Custom Design

Virtuosity: Is the Coloring Data Compliant with the MPT Flow?

In advanced node designs, to help you create designs that are compliant with the…

• 2 min read
Advanced Node , Multiple Patterning Technology , Virtuoso , Coloring Engine , Custom IC , Layout Editing

System, PCB, & Package Design 

How Do I Know What Functionality to Put on Which PCB Board?

There’s only so much you can do with a single printed circuit board (PCB). We’ve…

• 4 min read
PCB , multi-board systems , multiboard PCB , PCB design , multiboard systems , Multi-board PCB , Allegro

Breakfast Bytes

Texas Instruments on Automotive Reliability

Recently, I seem to have been running into people from Texas Instruments (TI) talking…

• 8 min read
Automotive , electromigration , functional safety , aging , Texas Instruments , fusa , reliability

Breakfast Bytes

Formal Signoff with JasperGold

At the recent Jasper User Group, I said that there were several themes. For overall…

• 5 min read
Jasper User Group , JUG , formal , signoff , JasperGold

Breakfast Bytes

Sunday Brunch Video for 28th October 2018

https://youtu.be/1vU3sg3QlWc Coming from building 8 lab (camera Sean) Monday: The…

• less than a min read
security , ARM Techcon , Jasper User Group , chiplets , formal , Jasper , 112g , SerDes , ARM , darpa , chips

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由之9：新设计规则检查

Allegro PCB 17.2-2016发行版增强了钻孔相关功能 我们为实际的钻孔工具、背钻工具、方形孔、沉头孔等增加了焊盘定义，并增加了钻孔容差。应广大用户需求…

• less than a min read
PCB , Chinese blog , Allegro 17.2 , PCB设计 , 中文 , Allegro PCB Editor , Allegro PCB编辑器 , Allegro升级17.2 , Allegro

Breakfast Bytes

ERI: CHIPS and Chiplets

One of the DARPA programs that is part of the Electronic Resurgence Initiative (ERI…

• 9 min read
chiplet , eri , darpa , chips

Verification

Cadence Announces Full Cadence Verification Suite Compatibility for Arm-Based High…

On October 16, 2018, Cadence Design Systems, Inc announced that, through a wide-reaching…

• 1 min read
press release , HPC , ARM , announcement

Analog/Custom Design

Virtuosity: Updated ADE Assembler and ADE Explorer Rapid Adoption Kit

The Virtuoso ADE Assembler and Virtuoso ADE Explorer Rapid Adoption Kit (RAK) has…

• 3 min read
ADE Explorer , Setup Library , Rapid Adoption Kit , Run Plan , ADE Verifier , IC6.1.8 , VVO , ADE Assembler

The India Circuit

An Ocean Of Opportunity

We were lucky to have Cadence CEO Lip-Bu Tan visit India recently, when he keynoted…

• 2 min read
artificial intelligence , CDNLive India , CDNLive , data driven economy , machine learning , Lip-Bu Tan , AI

Breakfast Bytes

Formal Post-Silicon Debug

Two outstanding presentations at the recent Jasper User Group were on using JasperGold…

• 6 min read
Jasper User Group , JUG , JasperGold

Whiteboard Wednesdays

Whiteboard Wednesdays - Cadence Unveils 112G Long-Reach SerDes IP in 7nm Technol…

With hyperscale datacenters requiring network switches delivering bandwidths of 12…

• less than a min read
Whiteboard Wednesdays , 100G Ethernet , 112G SerDes , PAM-4 , 400G Ethernet , 800G Ethernet

Breakfast Bytes

ERI: Hardware Security Workshop

The opening morning of DARPA's Electronic Resurgence Initiative summit in San Francisco…

• 8 min read
security , eri , darpa

System, PCB, & Package Design 

How To Maintain Connectivity in a Multi-Board PCB System

Today’s electronics often incorporate multiple interconnected printed circuit boards…

• 4 min read
PCB SI , PCB , multiboard PCB , PCB Signal integrity , PCB design , multiboard pcb system , multiboard systems

Breakfast Bytes

Arm TechCon: Get Ready for the NEOVERSE

I don't know if it was the vibe Arm's marketing was going for, but if you wanted…

• 5 min read
ARM Techcon , softbank , arm neoverse , ARM

Breakfast Bytes

The World's First Working 7nm 112G Long Reach SerDes Silicon

At the start of November last year, Cadence announced that it was acquiring nusemi…

• 6 min read
pam4 , 112g , semiconductor IP , SerDes , 7nm , datacenter

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由之8：过孔结构——下一代高速布线解决方案

过孔转换对信号布线来说十分常见。在高速设计中过孔转换是造成PCB互连中信号衰减的主要原因。而且高速通道需要地孔临近关键信号，在信号走线换层时，提供连续的回流路径…

• less than a min read
PCB , SI , Chinese blog , Allegro 17.2 , PCB设计 , 差分对支持 , 中文 , 信号完整性 , Allegro升级17.2 , SI分析与建模 , 高速 , 差分对
CDNS - Fix Layout Hompage