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Corporate News

New Ultra-Fast Debug Solution for Palladium Emulation with Verisium Debug

Verification engineers continually report that up to 70% of the total engineering…

Corporate
• 2 min read
news story , featured , verisium , AI

Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Analog/Custom Design

Things You Didn't Know About Virtuoso: ViVA (Part 2)

This week's installment, boys and girls, is brought to you by the letters H, V, m…

• 3 min read
ViVa-XL , IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Verification

OVM Innovation Means Business

Today, Cadence recognized it's OVM team for their innovative contribution to the…

• 2 min read
SystemVerilog , innovation , OVM ML , Functional Verification , OVM , OVM e , OVM SV , e , eRM , OVM SC , OVMWorld

Verification

Today's Innovation Awards and The "Trailblazer" Marathon

Today myself and the whole Trailblazer team are proud to celebrate the success of…

• 1 min read
innovation , Functional Verification , OVM , award , charity benefit

Digital Design

Cadence and Very Cool Stuff

One of the very cool things about my job is that I get to see all kinds of new stuff…

• 3 min read
PSO , innovation , MSV , Digital Implementation , FED

System, PCB, & Package Design 

What's Good About Innovation at Cadence? – It’s Alive and Well and Increasing!

I'm switching gears this week from my regular SPB technical product posts to focus…

• 3 min read
innovation , PCB design

Analog/Custom Design

Things You Wish You'd Thought Of...But You're Glad Someone Did!

On Tuesday this week we are celebrating "Innovation Day" here at Cadence, honoring…

• 1 min read
innovation , Custom IC Design

Verification

Emulation Is Here To Stay

A recent blog by Brian Bailey covered the emulation war. I would like to correct…

• 1 min read
System Design and Verification , Emulation

Verification

From Cadence Earning Call This Week

In system development, we have focused on two key customer challenges. First…

• 1 min read
TLM , NVIDIA , ITRI , Silicon Hive , System Design and Verification , OVM , Nethra Imaging , Rhode , Schwartz

Verification

Improve Productivity Through Communication and Learning

I regularly spend time talking to people about the importance of the connection between…

• 5 min read
System Design and Verification , CDNLive! 2009 Silicon Valley , Virtual Platforms , ISX

Verification

OVM Tricks and Treats

Your kids may be going house to house for treats, but you can get a big OVM sugar…

• 2 min read
SystemVerilog , OVM ML , Functional Verification , OVM , OVM e , OVM SV , e , AMIQ , IES , OVM SC

Verification

Why Verification Engineers Are Like Football Players

Is it their raw power? Is it the cheerleaders? Why are verification engineers like…

• less than a min read
performance , CDNLive , Functional Verification , OVM , Multi-Core , MDV , IES , IES-XL

Digital Design

Encounter How-To: Write Text to The Log File With "Puts"

Here's a simple but useful tip that shows how to write to the log file using the…

• 1 min read
EDI system , Digital Implementation , Encounter Digital Implementation , tcl

System, PCB, & Package Design 

What's Good About Net Color Override in Allegro? Check Out The SPB16.2 Release and…

Color assignment in Allegro PCB Editor has been accomplished with either a class…

• 1 min read
SPB 16.2 , color , Allegroro , PCB design

Verification

4 Minute Demo: OVM e Compliance Checks Added to AMIQ's DVT

Specmaniacs rejoice: long time Verification Alliance partner AMIQ has just added…

• less than a min read
eclipse , Specman , Functional Verification , OVM , OVM e , e , AMIQ

Verification

Where’s The “You” In The OVM?

Cadence and Mentor have dedicated teams to the development and support of the OVM…

• 2 min read
OVM ML , Functional Verification , OVM , OVM e , OVM SV , OVM Advisory Group , OVMWorld , IES-XL

Verification

4G Is Here Now

If you have not heard about 4G yet, it is here now. Verizon has already paid earlier…

• less than a min read
4G , System Design and Verification , Verizon , Rohde & Schwarz , Wimax , mobile

Analog/Custom Design

Things You Didn't Know About Virtuoso: ViVA

Sorry I've been missing from this space for so long. I've been busily working on…

• 3 min read
ViVa-XL , IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Verification

Keeping Trident Missiles "On Target" With System-Level Verification

Can you think of a more critical application for system-level verification than making…

• 1 min read
Mil-Aero , TLM , Draper Labs , System Design and Verification , Palladium

Digital Design

How To: Purge Interactive Constraints in MMMC Mode

These tips are applicable to the Encounter Digital Implementation System . Back in…

• 3 min read
timing constraints , Digital Implementation , mmmc , Encounter Digital Implementation System 8.1 , tcl
CDNS - Fix Layout Hompage