Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

Team Allegro Showing New PCB PDN Analysis Technology at DesignCon 2011

Today at DesignCon, drop by the Cadence booth to see TeamAllegro demonstrate the…

• 1 min read
PCB , PCB PI , PDN , PCB Signal and power integrity , Power Delivery Network , full wave , IR drop , power , Allegro

System, PCB, & Package Design 

Team Allegro to Boost Power of PCB PDN Solution – Sneak Peek at DesignCon 2011

The Cadence booth at DesignCon 2011 will provide visitors with a demonstration of…

• 1 min read
PCB , DesignCon , PCB PI , PDN , PCB Signal and power integrity , TeamAllegro , Power Delivery Network , full wave , IR drop , power , Allegro

Verification

What Could Be Simpler than a Request-Acknowledge Handshake?

My last few blog posts have included three corner-case conditions that led to bugs…

• 3 min read
Functional Verification , bugs , corner cases , formal , intent , assertions , simulation

Digital Design

Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End…

It hasn't been that long, but do you recall your new year's resolution? Eat healthier…

• 6 min read
ECO , conformal , Low Power , Encounter Test , gigahertz , giga-gate , 3D-IC , 3DIC , encounter digital implementation system , Mixed-Signal , encounter , rtl compiler , Silicon Realization , Digital Implementation , 3D , mixed signal , Digital end-to-end flow

Verification

The Role of Coverage in Formal Verification, Part 2 Continued…

Recall that three main questions need to be answered to attain coverage in formal…

• 3 min read
ABV , methodology , verification strategy , coverage , debug , Functional Verification , Formal Analysis , formal , Coverage-Driven Verification , CDV , Incisive , SVA , PSL , metric-driven verification , assertions , IEV , Incisive Enterprise Simulator (IES) , IFV

System, PCB, & Package Design 

What's Good About ADW’s Library Revision Manager and Browser? Check out the ADW16…

Here are just some of the new capabilities available in the ADW16.3 Allegro Design…

• less than a min read
PCB , SPB16.3 , Allegro Design Entry , DEHDL , Allegro 16.3 , SPB 16.3 , Allegro Design Workbench , Library flow , LRM , Design Entry HDL , component browser , design , Library Revision Manager , PCB design , Design Entry , ADW 16.3 , Librarians , ConceptHDL , library , Schematic , Allegro

Analog/Custom Design

SKILL for the Skilled: Continued Introduction to SKILL++

In my previous posting , which provided an introduction to SKILL++, I showed a simple…

• 6 min read
Team SKILL , hierarchy , walkCvHier , IC 6.1.5 , Virtuoso , flet , Lisp , Custom IC Design , SKILL++ , SKILL

Analog/Custom Design

Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 1)

There is no doubt in my mind that assertions will play a significant role in analog…

• 4 min read
SystemVerilog , AMS , ABV , assertion-based , coverage , analog , Constraint-driven , Mixed-Signal , SVA , Verilog , assertion , ADE-GXL , PSL , assertions , random , MDV , Custom IC Design

Verification

SystemC: It's Neither Complicated Nor Belligerent!

I was recently talking to a customer who was looking to move up in abstraction from…

• 2 min read
High-Level Synthesis , TLM , C to Silicon , system , SystemC , C++ , ESL , System Design and Verification

Verification

Video: Distinguished Engineer Alok Jain on Formal and Assertion-Based Verification…

Kicking off 2011, my colleague Alok Jain -- a Distinguished Engineer at Cadence who…

• less than a min read
Alok Jain , IP , ABV , verification strategy , metric driven verification (MDV) , Functional Verification , Formal Analysis , ABVIP , formal , EDA360 , Coverage-Driven Verification , CDV , assertions , MDV , IEV , Incisive Enterprise Simulator (IES) , IFV , verification

Verification

The Role of Coverage in Formal Verification, Part 2

As noted in the prior installment of this series, there are three main questions…

• 4 min read
ABV , methodology , verification strategy , coverage , Functional Verification , Formal Analysis , Model-checking , formal , Coverage-Driven Verification , Incisive , SVA , PSL , assertions , IEV , IFV , verification

System, PCB, & Package Design 

What's Good About PCB SI Model Library Management? Look to SPB16.3 and See!

The SPB16.3 release of Design Entry HDL (DEHDL) provides an easier method for setting…

• 2 min read
PCB SI , PCB , SCM , SI , SPB16.3 , Allegro Design Entry , diff pairs , Signal Intregrity , DEHDL , Allegro 16.3 , SPB 16.3 , property , Library flow , SPB , PCB Editor , Constraint Manager , ASA , Allegro System Architect (ASA) , Front-end PCB design , design , PCB Signal integrity , PCB design , Design Entry , differential pairs , SI analysis and modeling , File Directives , Differential Pair Support , ConceptHDL , dml , model editor , Schematic

Verification

Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog

A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and…

• 3 min read
SystemVerilog , Specman , OVM ML , Testbench simulation , OVM e , EDA , e , e language , team specman , Aspect Oriented Programming , eRM , simulation , AOP , Functional Verificatioa , IES-XL

Verification

Achieve the Next Level of Verification Productivity with Specman Advanced Option

Advanced verification customers are seeing their verification environments getting…

• 3 min read
Specman , Object Oriented Programming , debug , Functional Verification , Testbench simulation , e , e language , team specman , Aspect Oriented Programming , eRM , testbench , IES , AOP , verification , IES-XL , Trailblazer

Verification

In Verification, Failing to Plan = Planning to Fail

So I know you tell your kids this, you tell your spouse this, you heard it from…

• 2 min read
uvm , Verification methodology , metric driven verification (MDV) , Functional Verification , vPlan , MDV techtorial , verification planning , Incisive , Enterprise Manager , Enterprise Planner , FPGA , verification

System, PCB, & Package Design 

What's Good About APD Wire Bonding? SPB16.3 has MANY New Enhancements!

As with every new release, a primary focus for the Allegro Package Designer (APD…

• 14 min read
IC Packaging and SiP Design , SPB16.3 , IC Packaging , global route , Routing , Allegro 16.3 , layer stacks , SPB 16.3 , APD , SPB , PCB Editor , High-Density Interconnect , BGA , Layout , design , "PCB design" , PCB design

Verification

There's Another Simulation Failure! New SimVision Features Can Help

Simulation failures are seen quite often in design verification. Fortunately, with…

• 4 min read
uvm , debug , Functional Verification , simvision , Incisive , Silicon Realization

Verification

Applying Digital-Centric Verification Methodologies to Analog

A majority (if not all) SoCs today are mixed signal. Increasingly, the analog and…

• 4 min read
AMS , Low Power , Real Value Modeling , Functional Verification , Mixed Signal Verification , Mixed-Signal , metric-driven verification , SoC Connectivity , System Verification , Incisive Enterprise Simulator (IES) , IP modeling , RVM

Verification

My Reason For Choosing e – a Much More Advanced Verification Language. What’s Your…

I'd like to share with you a story from many, many, many moons ago when I first evaluated…

• 7 min read
SystemVerilog , Specman , debug , Functional Verification , e , e language , Aspect Oriented Programming , AOP
CDNS - Fix Layout Hompage