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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Using Scoreboards and Virtual Platforms for Software Verification

Today I'm running a guest article written by Henry Von Bank of Posedge Software …

• 4 min read
scoreboards , software verification , virtual platforms , posedge , virtual prototypes , Incisive , ISX , System Verification , linux

System, PCB, & Package Design 

What's Good About Differential Pairs in Allegro Constraint Manager? See For Yourself…

There are a couple new Differential Pair (Diff Pair) capabilities available with…

• 3 min read
PCB , PCB Layout and routing , DDR2 , SPB16.3 , Constraint-driven PCB Design flow , diff pairs , DRC , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , PCB design , differential Pair Swapping , reflection , Allegro PCB Editor , differential pairs , Differential Pair Support , library , Allegro

Verification

Verification Goldmine: 50 User Papers on Formal, Multi-Engine, and Assertion-Based…

With all due respect to our Tech Pubs writers, Solutions Architects, and contributors…

• 8 min read
verifier , DAC , ABV , methodology , CDNLive , metric driven verification (MDV) , debug , Functional Verification , Formal Analysis , formal , Incisive , SVA , Silicon Realization , PSL , DVcon , AMBA , MDV , IEV , IFV

Verification

CDNLive! Silicon Valley 2010 in the Rear-View Mirror

Well, we all survived another very busy CDNLive! event last week. Since I posted…

• 2 min read
uvm , CDNLive , OVM , EDA360 , MDV , techtorial , verification

Verification

User Views -- Migrating From FPGA-Based Prototyping to Palladium

In recent posting published by John Cooley on Deepchip.com, users compared FPGA-based…

• 1 min read
emulator , deepchip , prototyping , Palladium , Emulation , Cooley , FPGA

RF Engineering

Virtuoso APS Supports RF Analyses in MMSIM 7.2 and MMSIM 10.1

A new multi-threading capability has greatly improved simulation speed for RF Designers…

• less than a min read
RF , APS , MMSIMM , spectreRF , Spectre

System, PCB, & Package Design 

A Shorter, Predictable Design Cycle for Complex PCBs -- Electrical Constraint Sets…

This is the first in a series of blogs focused on how you can make your design cycle…

• 2 min read
PCB Layout and routing , DDR2 , ECSets , Constraint-driven PCB Design flow , Allegro 16.3 , XAUI , "PCB design" , PCB design , Allegro PCB Editor , Predictable PCB design , DDR3 , Allegro

Digital Design

CDNLive! Silicon Valley 2010: What EDA360 Means to Digital Implementation Engine…

CDNLive! Silicon Valley 2010 -- our user's group meeting and more -- kicked off yesterday…

• 4 min read
CDNLive , system realization , EDA360 , Silicon Realization , Digital Implementation , SoC Realization , CDNLive!

Verification

The Increasingly Hazardous World of FPGA Verification

Last week saw the publication of two interesting blog posts regarding the growing…

• 3 min read
uvm , Verification methodology , Functional Verification , Formal Analysis , OVM , FPGA

Verification

CDNLive! -- Israel and the U.S.

The Cadence Design Network provides a great way to learn about the latest design…

• 1 min read
CDNLive , system realization , Emulation , software , Israel , CDNLive! , embedded , System Design and Verification

Verification

Android, Linaro, and 10 Other Useful Embedded Linux Links

The state of Minnesota is unofficially divided into two parts; The Cities and The…

• 1 min read
android , System Design and Verification , linaro , software , linux , Embedded Linux , embedded

Verification

e Templates and e Macros -- An Update for Specman Users

A couple of recent blogs have mentioned the feature of e templates, which was added…

• 2 min read
Specman , Functional Verification , Incisive , e , team specman , macros , AOP , IES-XL

SoC and IP

Apple boots HDD--completely out of the new MacBook Air notebooks. SSD is the only…

Claiming that the move unifies Apple’s product line, Steve Jobs yesterday announced…

• less than a min read

Verification

Team Verify at CDNLive Silicon Valley Next Week – ABV, Formal, Multi-Engine Verification…

At next week's CDNLive! Silicon Valley in San Jose, California, Cadence will cover…

• 1 min read
NextOp , IP , ABV , methodology , Zocalo , CDNLive , Functional Verification , Formal Analysis , formal , EDA360 , Incisive , Silicon Realization , assertion synthesis , IEV , IFV

Verification

A Preview of Verification Sessions at CDNLive! Silicon Valley

As Cadence followers well know, our annual worldwide series of CDNLive! events is…

• 2 min read
uvm , ABV , CDNLive , OVM , MDV , techtorial , verification

System, PCB, & Package Design 

What's Good About Allegro Router and Via Changes? SPB16.3 Has a Few New Enhancements

This week, I’ll be closing discussions on the new SPB16.3 Allegro PCB Router improvements…

• 3 min read
PCB , PCB Layout and routing , SPB16.3 , Routing , specctra , Allegro 16.3 , layer stacks , SPB 16.3 , SPB , PCB Editor , Layout , via , PCB design , Allegro PCB Editor , microvia , Allegro

Digital Design

Five-Minute Tutorial: ecoAddRepeater

In today's tutorial, we're going to talk about the Encounter Digital Implementation…

• 3 min read
EDI system , tutorial , encounter , Digital Implementation , five minute , ecoAddRepeater

SoC and IP

Angelbird Ltd. Introduces “Wings,” a low-cost PCIe SSD for PCs. $239 for 16 Gbyt…

Stop me if you’ve heard this one. The fastest way to get high performance from an…

• less than a min read

SoC and IP

Hitachi-LG Data Storage fixes optical drive with SSD assist to use one SATA port

Hitachi-LG Data Storage has updated the hybrid optical/SSD drive it announced earlier…

• less than a min read
CDNS - Fix Layout Hompage