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Featured

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
Reela 2 Sep 2025 • 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
Virtuoso Release Team 27 Aug 2025 • 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
Corporate 21 Aug 2025 • 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
Vinod Khera 31 Jul 2025 • 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

  • All 6045
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  • Analog/Custom Design 760
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  • Learning and Support 55
  • RF Engineering 114
  • SoC and IP 407
  • System, PCB, & Package Design  982
  • Verification 1284
  • Cadence Japan 3

  • CFD(数値流体力学) 45
  • 中文技术专区 15
  • カスタムIC/ミックスシグナル 188
  • PCB、IC封装:设计与仿真分析 136
  • PCB解析/ICパッケージ解析 44
  • PCB設計/ICパッケージ設計 61
  • RF /マイクロ波設計 44
  • Spotlight Taiwan 61
  • The India Circuit 89
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List

Latest blogs

Digital Design

iSpatial: Next-Generation Common Physical Optimization Flow

With advanced-process nodes, a standard cell's physical delay, net delay, and congestion…

Neha Joshi 22 Mar 2021 • 1 min read
Genus , Logic Design , Synthesis , ispatial , physical implementation

Breakfast Bytes

DeepChip Best of 2020: Xcelium ML

Recently, I wrote about #2a on Cooley's Best of 2020 list, which was Cadence's vManager…

Paul McLellan 22 Mar 2021 • 3 min read
deepchip , xcelium ml , john cooley , verification

Breakfast Bytes

Sunday Brunch Video for 21st March 2021

https://youtu.be/i96zZHBFnTQ Made in my kitchen (camera Ziyue Zhang) Monday: The…

Paul McLellan 21 Mar 2021 • less than a min read
sunday brunch

System, PCB, & Package Design 

BoardSurfers: How to Create and Remove External DRCs using SKILL in PCB Editor

Design rules checks (DRC) determines whether your layout design complies with design…

Monika 18 Mar 2021 • 4 min read
17.4 , PCB design and layout , 17.4-2019 , PCB design , Allegro PCB Editor , SKILL

Breakfast Bytes

Offtopic: Man Wife Lung Slices (夫妻肺片)

Tomorrow is a Cadence global holiday. That's what it sounds like. Breakfast Bytes…

Paul McLellan 18 Mar 2021 • 6 min read
offtopic

PCB解析/ICパッケージ解析

Sigrity / Systems Analysis 2021.1 リリース(2021年2月) - 新機能ハイライト

SIGRITY から SIGRITY/SYSANLSへのリネーム SIGRITYリリースは、これからはSIGERITY/SYSANLSという名称で呼ばれることになります…

SPB Japan 18 Mar 2021 • 1 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , celsius , Clarity 3D Transient Solver , OrCAD/Allegro 17.4 (SPB174) , Sigrity , japanese blog , Sigrity 2021.1 , Clarity 3D Solver , Layout Workbench , clarity

カスタムIC/ミックスシグナル

Spectre Tech Tips: Spectre XDP-HB (Distributed HB) のご紹介

SPECTER 20.1.ISR4以降のリリースでは、新しいSpectre® X-RFシミュレーションテクノロジーの一部としてSpectre XDP-HBがリリースされました…

Custom IC Japan 17 Mar 2021 • less than a min read
Spectre RF , Spectre XDP-HB , Spectre X-RF , japanese blog , Spectre X distributed simulation

RF /マイクロ波設計

μWaveRiders:RF /マイクロ波の学生様向けCadence AWRの大学プログラム

Team RF "μWaveRiders" ブログシリーズがCadence AWR RF製品のためのショーケースとしてデビューします。月ごとの話題はCadence…

RF Design Japan 17 Mar 2021 • less than a min read
microwave , RF , AWR Analyst , Cadence Academic Network , AWR Design Environment , AWR AXIEM , RF design , AWR VSS , japanese blog , university program

RF Engineering

μWaveRiders: Cadence AWR University Program for RF/Microwave Students

For students in the RF/Microwave area of study, the Cadence AWR Design Environment…

TeamAWR 17 Mar 2021 • 4 min read
microwave , RF , AWR Analyst , Cadence Academic Network , AWR Design Environment , AWR AXIEM , RF design , AWR VSS , university program

Computational Fluid Dynamics

ETNZ Wins the America's Cup Once Again Using FINE/Marine

Once again Emirates Team New Zealand has entered the history books and won the America…

Paul McLellan 17 Mar 2021 • less than a min read
CFD , fine/marine , Computational Fluid Dynamics , NUMECA

Breakfast Bytes

DeepChip Best of 2020: vManager

We just finished 2020 (and let's hope 2021 is a better year). Every year, John Cooley…

Paul McLellan 17 Mar 2021 • 4 min read
deepchip , john cooley , vManager , verification

カスタムIC/ミックスシグナル

Virtuoso Meets Maxwell: Virtuoso RF ソリューション — フローの革命が次のレベルへ突入

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

Custom IC Japan 16 Mar 2021 • less than a min read
5G , IMS , integrand , SiP , pegusas , Virtuoso Overture , VRF , Celcius , awr , Virtuoso Meets Maxwell , Virtuoso System Design Environment , Virtuoso RF , Allegro Package Designer Plus , EMX , AWR AXIEM , RF design , SiP Layout Option , ICADVM20.1 , Sigrity , japanese blog , Quantus , Clarity 3D Solver , Custom IC Design , Allegro , VMM

Analog/Custom Design

Virtuoso Meets Maxwell: How to Simulate an RF Block with Passive and Active Devices…

Do you work with RF designs that contain both active and passive devices? Have you…

jgrad 16 Mar 2021 • 3 min read
AXIEM , VLS EXL , EM Solver , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic analysis , black boxing , Virtuoso , EMX , ICADVM20.1 , Clarity 3D Solver , Virtuoso Layout Suite EXL

Breakfast Bytes

Announcing Sigrity X

There are many different computational software algorithms used in EDA. One challenge…

Paul McLellan 16 Mar 2021 • 6 min read
x-technology , computational software , Signal Integrity , Sigrity

RF /マイクロ波設計

AWR製品の技術サポートがCadence Online Supportに移行されました!

2021年3月8日以降、AWR製品の技術サポートは標準のケイデンスサポートプロセスに移行されました。 このページは、この移行を通じてAWR製品のお客様を支援するトピックのコレクションです…

RF Design Japan 16 Mar 2021 • less than a min read
AWR Design Environment , awr , japanese blog

定制IC芯片设计

Virtuoso Meets Maxwell:跨结构电磁提取功能- 简化IC、封装和电路板耦合的任务

当您在设计RFICs或RF模块时,如果只分析IC或模块上的电磁行为,那么可能会造成结果缺失。即使IC的电磁行为已达到其规格要求,也很容易将其耦合至模块周边的走线上…

jgrad 15 Mar 2021 • 1 min read
Chinese blog , Virtuoso ICADVM20.1 , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Electromagnetic analysis , Virtuoso , Custom IC Design , Virtuoso Layout Suite

Breakfast Bytes

The History of PCIe: Getting to Version 6

PCIe, or Peripheral Component Interconnect Express which nobody ever says, was an…

Paul McLellan 15 Mar 2021 • 6 min read
pcie gen 5 , PCIe

Breakfast Bytes

Sunday Brunch Video for 14th March 2021

https://youtu.be/bzgotynPvs8 Made at Fry's Electronics in San Jose (camera Ziyue…

Paul McLellan 14 Mar 2021 • less than a min read
sunday brunch

Academic Network

Expanding Our Network — AWR Academic Partners

We want to continue highlighting the amazing AWR academic connections! We’ll be covering…

Kira Jones 12 Mar 2021 • 6 min read
Lead Institutions , Cadence Academic Network , awr , University of Bristol , university program
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