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Featured

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
MBhatnagar 22 Sep 2025 • 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
Corporate 20 Sep 2025 • 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
Corporate 17 Sep 2025 • 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
Reela Samuel 2 Sep 2025 • 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

Whiteboard Wednesdays

Whiteboard Wednesdays - LPDDR4X DRAM: Performance and Power Efficiency Improvements…

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty will help you learn…

References4U 30 Jan 2018 • less than a min read
Whiteboard Wednesdays , LPDDR4

Breakfast Bytes

All Models Are Wrong; Some Are Useful

"All models are wrong, some are useful.” This remark is attributed to the statistician…

Paul McLellan 30 Jan 2018 • 9 min read
climate , model , digital , SPICE

Verification

JEDEC UFS 3.0 Now Available in Cadence VIP Portfolio – For Mobile and Automotive…

The JEDEC UFS (Universal Flash Storage) started in 2011 with the v1.0 first specification…

Thierry Berdah 29 Jan 2018 • 1 min read
Verification IP , UniPro , MIPI Alliance , JEDEC , automotive electronics , UFS , storage , MPHY

Breakfast Bytes

TSMC 30 Years Ago Today

At IEDM in December, Gary Dagastine is one of the people responsible for press relations…

Paul McLellan 28 Jan 2018 • 6 min read
Taiwan , fabless , TSMC , chips and technologies , foundry

The India Circuit

The Promise Of Digital India

By 2019, it is estimated that there will be five billion mobile phone users in the…

Madhavi Rao 28 Jan 2018 • 4 min read
Narendra Modi , digital india , National Digital Literacy Mission , Aadhar , Ravi Shanker Prasad

Breakfast Bytes

City Slickers Marketing

Last week I talked about sales in Running a Salesforce . This week it is the turn…

Paul McLellan 26 Jan 2018 • 4 min read
steve blank , city slickers marketing , marketing

Whiteboard Wednesdays

Whiteboard Wednesdays - Verification Challenges for SoCs Integrating CCIX Interface…

In this week's Whiteboard Wednesdays episode, Nick Heaton, Distinguished Engineer…

References4U 25 Jan 2018 • less than a min read
Whiteboard Wednesdays , ccix

Computational Fluid Dynamics

Morrelli & Melvin: Making Waves in the Marine Industry with Numeca for Hydrofoil…

Numeca USA customer Morrelli & Melvin has been busy using FINE/Marine for various…

AnneMarie CFD 25 Jan 2018 • 3 min read

Computational Fluid Dynamics

Morrelli & Melvin: Making Waves in the Marine Industry with Numeca for Hydrofoil…

Numeca USA customer Morrelli & Melvin has been busy using FINE /Marine for various…

Tanushri Shah 25 Jan 2018 • 4 min read

Breakfast Bytes

Coventor Annual Panel: The Next Five Years

For the last few years at IEDM, Coventor have run an evening panel session looking…

Paul McLellan 25 Jan 2018 • 8 min read
asml , KLA-Tencor , Lam Research , nova , Coventor , GlobalFoundries , IEDM

Verification

Type MIN / MAX Values in Specman

When defining coverage bins for coverage items, the number and size of bins depend…

teamspecman 25 Jan 2018 • 3 min read
Specman , Specman coverage engine , Specman e

Verification

App Note Spotlight: SystemVerilog Gets a Real Number Modeling Update (SVRNM)

Thanks to Xcelium, there’s a new feature on the block in SystemVerilog. It pertains…

XTeam 24 Jan 2018 • 1 min read
SystemVerilog , real number modeling , Functional Verification , App Note Spotlight

Verification

CCIX Coherency: Verification Challenges and Approaches

Cache coherency is not a new concept. Coherent architectures have existed for many…

DimitryP 24 Jan 2018 • 2 min read
Verification IP , ccix , SoC , coherency , System Verification

Breakfast Bytes

Passwords: Just Add Salt

This is a second post about passwords, picking up where Passwords: How Even Your…

Paul McLellan 24 Jan 2018 • 5 min read
security , password , two-factor authentication , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview January 29th to February 2nd 2018

https://youtu.be/OtFTlu1u9xI Coming from TSMC North America (camera Sean) Monday…

Paul McLellan 23 Jan 2018 • less than a min read
DesignCon , Models , TSMC , semiconductor IP , open source

Breakfast Bytes

Passwords: How Even Your Bank Doesn't Know Your PIN

In my predictions for 2018 piece yesterday, Nibbles: Breakfast Bytes Predictions…

Paul McLellan 23 Jan 2018 • 7 min read
cryptographic hash , passwords , salt , hashing

Breakfast Bytes

Nibbles: Breakfast Bytes Predictions for 2018

Every year Breakfast Bytes makes some predictions for the year. At the end of the…

Paul McLellan 22 Jan 2018 • 7 min read
security , Automotive , 5nm , autonomous vehicles , EUV

Analog/Custom Design

Virtuosity:Expression Builder - Now Plots ALL!

The Expression Builder has simplified writing complex expressions and has the ability…

Arja H 19 Jan 2018 • 2 min read
ADE Explorer , ADE , Expression Builder , Virtuoso , ViVA , Virtuosity , ADE Assembler

Breakfast Bytes

Running a Salesforce

I decided to run some posts on different areas of companies, and what I have found…

Paul McLellan 19 Jan 2018 • 10 min read
sales , salesforce , business development , sales management
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