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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

Breakfast Bytes

Why Don't Planes Obey Moore's Law?

In my post about Silexica ( Silexica: Mastering Multicore ) I said that I like to…

• 9 min read
great flight diagram , aeronautics , tennekes , flight , simple science of flight

Analog/Custom Design

Virtuosity: From Hatchlings to Fledglings to a Flock of Birds Blogging Together

“The reason birds can fly and we can't is simply because they have perfect faith…

• 2 min read
Cadence blogs , Virtuoso , RF design , Virtuosity , Virtuoso Video Diary , CPG Technical Communications Engineering

Breakfast Bytes

Blue LEDs, Nobel Prizes, and IEDM Keynote

At IEDM last week, for the first time, there was a second plenary session (awards…

• 6 min read
gallium nitride , nobel prize , Wally Rhines , LED , blue led , gan , IEDM

Breakfast Bytes

Ploughing 1 TB of RAM with Twenty x86 Oxen and 10,000 RISC-V Chickens

OK, that wins the prize for best title of a presentation in the recent RISC-V workshop…

• 11 min read
risc-v , celerity , boom , picochip , risc-v foundation , esperanto , sifive

Whiteboard Wednesdays

Whiteboard Wednesdays - What to expect from TLM 2.0 Models for Memory Subsystems…

In this week's Whiteboard Wednesday, Vivek Nandakumar explains the behavioral differences…

• less than a min read
Whiteboard Wednesdays , Memory , TLM 2.0

Breakfast Bytes

RISC-V Workshop, Milpitas

The latest semi-annual RISC-V workshop took place the week after Thanksgiving. The…

• 8 min read
Western Digital , risc-v , celerity , boom , picochip , risc-v foundation , esperanto , 16nm , 7nm

Learning and Support

What's New in Cadence Help 3.0?

I am sure you would agree when I say that a help tool is the one utility without…

• 3 min read
Self-Help , Cadence Help , Help resource , Cadence support

Breakfast Bytes

COTS? Commercial Products in US Government Electronics

COTS is government jargon for Commercial Off-The-Shelf. This means the government…

• 8 min read
us government , minsec , department of defense

The India Circuit

Four Exciting Examples of Modern AI from NVIDIA

A few months ago, we had the honor of having Vishal Dhupar, Managing Director of…

• 4 min read
artificial intelligence , deep learning , NVIDIA , machine learning , AI

Analog/Custom Design

Virtuosity: SKILLful Virtuoso Visualization and Analysis

If you’re a SKILL enthusiast, you’ll be happy to know that the latest IC6.1.7 ISR…

• 4 min read
Analog Design Environment , ViVa-XL , custom/analog , Analog Simulation , SKILL for the Skilled , ADE , Virtuoso , ViVA , Virtuosity , Custom IC Design , SKILL , Cusstom IC Design

Breakfast Bytes

IEDM 2017

The start of December means it is the International Electron Devices Meeting in San…

• 6 min read
Intel , copper beol , 3D IC , AMD , georgia tech , Samsung , TSMC , fanout wafer packaging , GlobalFoundries

Analog/Custom Design

Virtuosity: Can I Graphically Edit Width Spacing Patterns?

We have enhanced the editing modes available for WSPs. In addition to the text-based…

• 1 min read
Routing , Advanced Node , width spacing patterns , Layout , Virtuoso , Virtuosity , Custom IC Design

Academic Network

2017 Workshop on Electronic Design Automation in Tainan Taiwan

It was the third continuous year that Cadence Academic Network supported the Workshop…

• 1 min read
Taiwan , Cadence Academic Network , EDA

Breakfast Bytes

Greg Yeric and Rob Aitken Dive into the Details

The last day of TechCon had two keynotes rich in deeper technical content, from Greg…

• 6 min read
security , greg yeric , graphen , IoT , trillion devices , Rob Aitken , more than Moore , moore's law , power

Breakfast Bytes

Advanced Packaging Delivers More Than Moore

Moore's Law is running out of steam. Depending on your point of view, it is dead…

• 8 min read
FOWLP , advanced packaging , 3DIC , Virtuoso , OrbitIO , Innovus , 2.5D , Allegro

Digital Design

Get Early Silicon Learning to Accelerate Yield Ramp-up

How important is it for your advanced node products to get early silicon learning…

• 2 min read
DNA , pattern analysis , machine learning , silicon learning , yield , test chip , design for manufacturing , DFM

Whiteboard Wednesdays

Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 2

In this week's Whiteboard Wednesday, Tom Hackett continues his explanation of neural…

• less than a min read
Whiteboard Wednesdays , neural networks

Analog/Custom Design

Virtuosity: Can I Plot Signals with Different Axis Units in the Same Window?

Have you been frustrated trying to drag signals around in Virtuoso Visualization…

• 1 min read
virtuoso visualization and analysis , Virtuoso Analog Design Environment , Analog Design Environment , ViVA

Breakfast Bytes

Supercomputers

HPC, or high-performance computing, is one of the big focus areas for semiconductors…

• 9 min read
Intel , top 500 list , top500 , supercomputer
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